118 lines
4.3 KiB
Verilog
118 lines
4.3 KiB
Verilog
`include "VX_define.vh"
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module VX_mem_arb #(
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parameter NUM_REQS = 1,
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parameter DATA_WIDTH = 1,
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parameter TAG_IN_WIDTH = 1,
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parameter TAG_OUT_WIDTH = 1,
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parameter BUFFERED_REQ = 0,
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parameter BUFFERED_RSP = 0,
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parameter DATA_SIZE = (DATA_WIDTH / 8),
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parameter ADDR_WIDTH = 32 - `CLOG2(DATA_SIZE),
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parameter LOG_NUM_REQS = `CLOG2(NUM_REQS)
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) (
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input wire clk,
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input wire reset,
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// input requests
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input wire [NUM_REQS-1:0] req_valid_in,
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input wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] req_tag_in,
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input wire [NUM_REQS-1:0][ADDR_WIDTH-1:0] req_addr_in,
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input wire [NUM_REQS-1:0] req_rw_in,
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input wire [NUM_REQS-1:0][DATA_SIZE-1:0] req_byteen_in,
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input wire [NUM_REQS-1:0][DATA_WIDTH-1:0] req_data_in,
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output wire [NUM_REQS-1:0] req_ready_in,
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// output request
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output wire req_valid_out,
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output wire [TAG_OUT_WIDTH-1:0] req_tag_out,
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output wire [ADDR_WIDTH-1:0] req_addr_out,
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output wire req_rw_out,
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output wire [DATA_SIZE-1:0] req_byteen_out,
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output wire [DATA_WIDTH-1:0] req_data_out,
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input wire req_ready_out,
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// input response
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input wire rsp_valid_in,
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input wire [TAG_OUT_WIDTH-1:0] rsp_tag_in,
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input wire [DATA_WIDTH-1:0] rsp_data_in,
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output wire rsp_ready_in,
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// output responses
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output wire [NUM_REQS-1:0] rsp_valid_out,
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output wire [NUM_REQS-1:0][TAG_IN_WIDTH-1:0] rsp_tag_out,
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output wire [NUM_REQS-1:0][DATA_WIDTH-1:0] rsp_data_out,
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input wire [NUM_REQS-1:0] rsp_ready_out
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);
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localparam REQ_DATAW = TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH;
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localparam RSP_DATAW = TAG_IN_WIDTH + DATA_WIDTH;
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if (NUM_REQS > 1) begin
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wire [NUM_REQS-1:0][REQ_DATAW-1:0] req_merged_data_in;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign req_merged_data_in[i] = {{req_tag_in[i], LOG_NUM_REQS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]};
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end
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VX_stream_arbiter #(
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.NUM_REQS (NUM_REQS),
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.DATAW (REQ_DATAW),
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.BUFFERED (BUFFERED_REQ)
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) req_arb (
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.clk (clk),
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.reset (reset),
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.valid_in (req_valid_in),
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.data_in (req_merged_data_in),
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.ready_in (req_ready_in),
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.valid_out (req_valid_out),
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.data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}),
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.ready_out (req_ready_out)
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);
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///////////////////////////////////////////////////////////////////////
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wire [LOG_NUM_REQS-1:0] rsp_sel = rsp_tag_in [LOG_NUM_REQS-1:0];
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wire [NUM_REQS-1:0][RSP_DATAW-1:0] rsp_merged_data_out;
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for (genvar i = 0; i < NUM_REQS; i++) begin
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assign {rsp_tag_out[i], rsp_data_out[i]} = rsp_merged_data_out[i];
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end
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VX_stream_demux #(
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.NUM_REQS (NUM_REQS),
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.DATAW (RSP_DATAW),
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.BUFFERED (BUFFERED_RSP)
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) rsp_demux (
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.clk (clk),
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.reset (reset),
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.sel (rsp_sel),
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.valid_in (rsp_valid_in),
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.data_in ({rsp_tag_in[LOG_NUM_REQS +: TAG_IN_WIDTH], rsp_data_in}),
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.ready_in (rsp_ready_in),
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.valid_out (rsp_valid_out),
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.data_out (rsp_merged_data_out),
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.ready_out (rsp_ready_out)
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);
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end else begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign req_valid_out = req_valid_in;
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assign req_tag_out = req_tag_in;
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assign req_addr_out = req_addr_in;
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assign req_rw_out = req_rw_in;
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assign req_byteen_out = req_byteen_in;
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assign req_data_out = req_data_in;
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assign req_ready_in = req_ready_out;
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assign rsp_valid_out = rsp_valid_in;
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assign rsp_tag_out = rsp_tag_in;
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assign rsp_data_out = rsp_data_in;
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assign rsp_ready_in = rsp_ready_out;
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end
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endmodule |