90e21e8e58
It seems many of the initial arch/uarch states, including the GPR, are uninitialized in the VCS simulation, which results in functional errors caused by propagated X's. In this particular case it resulted in a dcache request not being fired due to the rs1 data for an lw instruction having values as X, causing the smem_unit to not arbitrate the request correctly. A workaround of this issue is to stop the X propagation by using the ===-operation instead of == in the GPR unit, which had been the main source of X propagation into the raddr port of the GPR. Also, we run the simulation with GSR_RESET set to 1 so that the contents of the GPR are initialized at the beginning of the simulation (however, this alone does not prevent reading in X's, hence this fix.) FIXME: This is a slight deviation from the upstream code; ideally, we want to do clean & full initialization of microarchitectural states.
315 lines
11 KiB
Systemverilog
315 lines
11 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_dp_ram #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter WRENW = 1,
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parameter OUT_REG = 0,
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parameter NO_RWCHECK = 0,
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parameter LUTRAM = 0,
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parameter INIT_ENABLE = 0,
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parameter INIT_FILE = "",
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parameter [DATAW-1:0] INIT_VALUE = 0,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire read,
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input wire write,
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input wire [WRENW-1:0] wren,
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input wire [ADDRW-1:0] waddr,
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input wire [DATAW-1:0] wdata,
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input wire [ADDRW-1:0] raddr,
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output wire [DATAW-1:0] rdata
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);
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localparam WSELW = DATAW / WRENW;
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`STATIC_ASSERT((WRENW * WSELW == DATAW), ("invalid parameter"))
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`define RAM_INITIALIZATION \
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if (INIT_ENABLE != 0) begin \
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if (INIT_FILE != "") begin \
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initial $readmemh(INIT_FILE, ram); \
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end else begin \
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initial \
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for (integer i = 0; i < SIZE; ++i) \
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ram[i] = INIT_VALUE; \
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end \
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end
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`UNUSED_VAR (read)
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`ifdef SYNTHESIS
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if (WRENW > 1) begin
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`ifdef QUARTUS
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if (LUTRAM != 0) begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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`USE_FAST_BRAM reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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end
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assign rdata = ram[raddr];
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end
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK != 0) begin
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`NO_RW_RAM_CHECK reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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end
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assign rdata = ram[raddr];
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end else begin
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reg [WRENW-1:0][WSELW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i] <= wdata[i * WSELW +: WSELW];
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end
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end
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end
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assign rdata = ram[raddr];
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end
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end
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end
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`else
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// default synthesis
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if (LUTRAM != 0) begin
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`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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end
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assign rdata = ram[raddr];
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end
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] rdata_r;
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK != 0) begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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end
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assign rdata = ram[raddr];
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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for (integer i = 0; i < WRENW; ++i) begin
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if (wren[i])
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ram[waddr][i * WSELW +: WSELW] <= wdata[i * WSELW +: WSELW];
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end
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end
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end
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assign rdata = ram[raddr];
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end
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end
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end
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`endif
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end else begin
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// (WRENW == 1)
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if (LUTRAM != 0) begin
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`USE_FAST_BRAM reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= wdata;
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= wdata;
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end
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end
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assign rdata = ram[raddr];
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end
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end else begin
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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reg [DATAW-1:0] rdata_r;
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= wdata;
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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if (NO_RWCHECK != 0) begin
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`NO_RW_RAM_CHECK reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= wdata;
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end
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end
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assign rdata = ram[raddr];
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end else begin
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reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= wdata;
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end
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end
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assign rdata = ram[raddr];
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end
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end
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end
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end
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`else
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// RAM emulation
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reg [DATAW-1:0] ram [SIZE-1:0];
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`RAM_INITIALIZATION
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wire [DATAW-1:0] ram_n;
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for (genvar i = 0; i < WRENW; ++i) begin
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assign ram_n[i * WSELW +: WSELW] = ((WRENW == 1) | wren[i]) ? wdata[i * WSELW +: WSELW] : ram[waddr][i * WSELW +: WSELW];
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end
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if (OUT_REG != 0) begin
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reg [DATAW-1:0] rdata_r;
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= ram_n;
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end
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if (read) begin
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rdata_r <= ram[raddr];
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end
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end
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assign rdata = rdata_r;
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end else begin
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reg [DATAW-1:0] prev_data;
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reg [ADDRW-1:0] prev_waddr;
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reg prev_write;
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always @(posedge clk) begin
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if (write) begin
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ram[waddr] <= ram_n;
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end
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prev_write <= (| wren);
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prev_data <= ram[waddr];
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prev_waddr <= waddr;
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end
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if (LUTRAM || !NO_RWCHECK) begin
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`UNUSED_VAR (prev_write)
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`UNUSED_VAR (prev_data)
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`UNUSED_VAR (prev_waddr)
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assign rdata = ram[raddr];
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end else begin
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assign rdata = (prev_write && (prev_waddr === raddr)) ? prev_data : ram[raddr];
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end
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end
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`endif
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endmodule
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`TRACING_ON
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