d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
293 lines
10 KiB
Systemverilog
293 lines
10 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_fpu_define.vh"
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`ifdef FPU_DSP
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/// Modified port of noncomp module from fpnew Libray
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/// reference: https://github.com/pulp-platform/fpnew
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module VX_fpu_ncomp import VX_fpu_pkg::*; #(
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parameter NUM_LANES = 1,
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parameter TAGW = 1
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) (
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input wire clk,
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input wire reset,
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output wire ready_in,
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input wire valid_in,
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input wire [NUM_LANES-1:0] lane_mask,
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input wire [TAGW-1:0] tag_in,
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input wire [`INST_FPU_BITS-1:0] op_type,
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input wire [`INST_FRM_BITS-1:0] frm,
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input wire [NUM_LANES-1:0][31:0] dataa,
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input wire [NUM_LANES-1:0][31:0] datab,
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output wire [NUM_LANES-1:0][31:0] result,
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output wire has_fflags,
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output wire [`FP_FLAGS_BITS-1:0] fflags,
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output wire [TAGW-1:0] tag_out,
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input wire ready_out,
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output wire valid_out
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);
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localparam EXP_BITS = 8;
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localparam MAN_BITS = 23;
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localparam NEG_INF = 32'h00000001,
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NEG_NORM = 32'h00000002,
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NEG_SUBNORM = 32'h00000004,
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NEG_ZERO = 32'h00000008,
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POS_ZERO = 32'h00000010,
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POS_SUBNORM = 32'h00000020,
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POS_NORM = 32'h00000040,
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POS_INF = 32'h00000080,
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//SIG_NAN = 32'h00000100,
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QUT_NAN = 32'h00000200;
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wire [NUM_LANES-1:0] a_sign, b_sign;
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wire [NUM_LANES-1:0][7:0] a_exponent, b_exponent;
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wire [NUM_LANES-1:0][22:0] a_mantissa, b_mantissa;
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fclass_t [NUM_LANES-1:0] a_fclass, b_fclass;
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wire [NUM_LANES-1:0] a_smaller, ab_equal;
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// Setup
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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assign a_sign[i] = dataa[i][31];
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assign a_exponent[i] = dataa[i][30:23];
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assign a_mantissa[i] = dataa[i][22:0];
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assign b_sign[i] = datab[i][31];
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assign b_exponent[i] = datab[i][30:23];
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assign b_mantissa[i] = datab[i][22:0];
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VX_fpu_class #(
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.EXP_BITS (EXP_BITS),
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.MAN_BITS (MAN_BITS)
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) fp_class_a (
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.exp_i (a_exponent[i]),
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.man_i (a_mantissa[i]),
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.clss_o (a_fclass[i])
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);
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VX_fpu_class #(
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.EXP_BITS (EXP_BITS),
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.MAN_BITS (MAN_BITS)
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) fp_class_b (
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.exp_i (b_exponent[i]),
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.man_i (b_mantissa[i]),
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.clss_o (b_fclass[i])
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);
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assign a_smaller[i] = (dataa[i] < datab[i]) ^ (a_sign[i] || b_sign[i]);
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assign ab_equal[i] = (dataa[i] == datab[i])
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|| (a_fclass[i].is_zero && b_fclass[i].is_zero); // +0 == -0
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end
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// Pipeline stage0
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wire valid_in_s0;
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wire [NUM_LANES-1:0] lane_mask_s0;
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wire [TAGW-1:0] tag_in_s0;
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wire [3:0] op_mod_s0;
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wire [NUM_LANES-1:0][31:0] dataa_s0, datab_s0;
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wire [NUM_LANES-1:0] a_sign_s0, b_sign_s0;
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wire [NUM_LANES-1:0][7:0] a_exponent_s0;
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wire [NUM_LANES-1:0][22:0] a_mantissa_s0;
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fclass_t [NUM_LANES-1:0] a_fclass_s0, b_fclass_s0;
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wire [NUM_LANES-1:0] a_smaller_s0, ab_equal_s0;
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wire stall;
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wire [3:0] op_mod = {(op_type == `INST_FPU_CMP), frm};
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VX_pipe_register #(
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.DATAW (1 + NUM_LANES + TAGW + 4 + NUM_LANES * (2 * 32 + 1 + 1 + 8 + 23 + 2 * $bits(fclass_t) + 1 + 1)),
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.RESETW (1)
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) pipe_reg0 (
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.clk (clk),
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.reset (reset),
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.enable (!stall),
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.data_in ({valid_in, lane_mask, tag_in, op_mod, dataa, datab, a_sign, b_sign, a_exponent, a_mantissa, a_fclass, b_fclass, a_smaller, ab_equal}),
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.data_out ({valid_in_s0, lane_mask_s0, tag_in_s0, op_mod_s0, dataa_s0, datab_s0, a_sign_s0, b_sign_s0, a_exponent_s0, a_mantissa_s0, a_fclass_s0, b_fclass_s0, a_smaller_s0, ab_equal_s0})
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);
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// FCLASS
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reg [NUM_LANES-1:0][31:0] fclass_mask_s0; // generate a 10-bit mask for integer reg
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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always @(*) begin
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if (a_fclass_s0[i].is_normal) begin
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fclass_mask_s0[i] = a_sign_s0[i] ? NEG_NORM : POS_NORM;
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end
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else if (a_fclass_s0[i].is_inf) begin
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fclass_mask_s0[i] = a_sign_s0[i] ? NEG_INF : POS_INF;
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end
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else if (a_fclass_s0[i].is_zero) begin
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fclass_mask_s0[i] = a_sign_s0[i] ? NEG_ZERO : POS_ZERO;
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end
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else if (a_fclass_s0[i].is_subnormal) begin
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fclass_mask_s0[i] = a_sign_s0[i] ? NEG_SUBNORM : POS_SUBNORM;
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end
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else if (a_fclass_s0[i].is_nan) begin
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fclass_mask_s0[i] = {22'h0, a_fclass_s0[i].is_quiet, a_fclass_s0[i].is_signaling, 8'h0};
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end
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else begin
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fclass_mask_s0[i] = QUT_NAN;
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end
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end
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end
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// Min/Max
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reg [NUM_LANES-1:0][31:0] fminmax_res_s0;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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always @(*) begin
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if (a_fclass_s0[i].is_nan && b_fclass_s0[i].is_nan)
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fminmax_res_s0[i] = {1'b0, 8'hff, 1'b1, 22'd0}; // canonical qNaN
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else if (a_fclass_s0[i].is_nan)
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fminmax_res_s0[i] = datab_s0[i];
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else if (b_fclass_s0[i].is_nan)
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fminmax_res_s0[i] = dataa_s0[i];
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else begin
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// FMIN, FMAX
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fminmax_res_s0[i] = (op_mod_s0[0] ^ a_smaller_s0[i]) ? dataa_s0[i] : datab_s0[i];
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end
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end
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end
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// Sign injection
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reg [NUM_LANES-1:0][31:0] fsgnj_res_s0; // result of sign injection
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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always @(*) begin
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case (op_mod_s0[1:0])
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0: fsgnj_res_s0[i] = { b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]};
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1: fsgnj_res_s0[i] = {~b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]};
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default: fsgnj_res_s0[i] = { a_sign_s0[i] ^ b_sign_s0[i], a_exponent_s0[i], a_mantissa_s0[i]};
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endcase
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end
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end
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// Comparison
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reg [NUM_LANES-1:0] fcmp_res_s0; // result of comparison
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reg [NUM_LANES-1:0] fcmp_fflags_NV_s0; // comparison fflags
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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always @(*) begin
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case (op_mod_s0[1:0])
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0: begin // LE
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if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
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fcmp_res_s0[i] = 0;
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fcmp_fflags_NV_s0[i] = 1;
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end else begin
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fcmp_res_s0[i] = (a_smaller_s0[i] | ab_equal_s0[i]);
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fcmp_fflags_NV_s0[i] = 0;
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end
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end
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1: begin // LT
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if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
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fcmp_res_s0[i] = 0;
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fcmp_fflags_NV_s0[i] = 1;
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end else begin
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fcmp_res_s0[i] = (a_smaller_s0[i] & ~ab_equal_s0[i]);
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fcmp_fflags_NV_s0[i] = 0;
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end
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end
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2: begin // EQ
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if (a_fclass_s0[i].is_nan || b_fclass_s0[i].is_nan) begin
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fcmp_res_s0[i] = 0;
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fcmp_fflags_NV_s0[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
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end else begin
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fcmp_res_s0[i] = ab_equal_s0[i];
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fcmp_fflags_NV_s0[i] = 0;
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end
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end
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default: begin
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fcmp_res_s0[i] = 'x;
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fcmp_fflags_NV_s0[i] = 'x;
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end
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endcase
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end
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end
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// outputs
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reg [NUM_LANES-1:0][31:0] result_s0;
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reg [NUM_LANES-1:0] fflags_NV_s0;
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for (genvar i = 0; i < NUM_LANES; ++i) begin
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always @(*) begin
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case (op_mod_s0[2:0])
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0,1,2: begin
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// SGNJ, CMP
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result_s0[i] = op_mod_s0[3] ? 32'(fcmp_res_s0[i]) : fsgnj_res_s0[i];
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fflags_NV_s0[i] = fcmp_fflags_NV_s0[i];
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end
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3: begin
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// CLASS
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result_s0[i] = fclass_mask_s0[i];
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fflags_NV_s0[i] = 'x;
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end
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4,5: begin
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// FMV
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result_s0[i] = dataa_s0[i];
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fflags_NV_s0[i] = 'x;
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end
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6,7: begin
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// MIN/MAX
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result_s0[i] = fminmax_res_s0[i];
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fflags_NV_s0[i] = a_fclass_s0[i].is_signaling | b_fclass_s0[i].is_signaling;
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end
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endcase
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end
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end
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// only MIN/MAX and CMP return status flags
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wire has_fflags_s0 = (op_mod_s0[2:0] >= 6) || op_mod_s0[3];
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assign stall = ~ready_out && valid_out;
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wire fflags_NV;
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reg fflags_merged;
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always @(*) begin
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fflags_merged = 0;
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for (integer i = 0; i < NUM_LANES; ++i) begin
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if (lane_mask_s0[i]) begin
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fflags_merged |= fflags_NV_s0[i];
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end
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end
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end
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VX_pipe_register #(
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.DATAW (1 + TAGW + (NUM_LANES * 32) + 1 + 1),
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.RESETW (1)
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) pipe_reg1 (
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.clk (clk),
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.reset (reset),
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.enable (!stall),
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.data_in ({valid_in_s0, tag_in_s0, result_s0, has_fflags_s0, fflags_merged}),
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.data_out ({valid_out, tag_out, result, has_fflags, fflags_NV})
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);
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assign ready_in = ~stall;
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// NV, DZ, OF, UF, NX
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assign fflags = {fflags_NV, 1'b0, 1'b0, 1'b0, 1'b0};
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endmodule
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`endif
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