Blaise Tine 97739e9dcf RAM blocks inference fixes

2020-11-30 14:02:47 -08:00

..

cache

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

core

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

pipeline

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

top

scope refactoring: adding modules definitions to VCD trace

2020-10-12 23:26:02 -04:00

vortex

pipeline refactoring - fmax >= 222 mhz

2020-08-14 21:50:14 -07:00

.gitignore

minor update

2020-06-29 15:09:14 -07:00

project.sdc

fp_noncomp fixes

2020-08-23 16:53:28 -07:00

project.tcl

RAM blocks inference fixes

2020-11-30 14:02:47 -08:00

timing.tcl

fixed FPU handshake, optimized writeback's critical path

2020-08-07 10:11:54 -07:00