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97739e9dcffcd2db2f3ff1aef0a4f66993b9fb6e
vortex/hw/rtl/cache
History
Blaise Tine 97739e9dcf RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
..
VX_bank_core_req_arb.v
reset networks optimization
2020-11-16 01:12:02 -08:00
VX_bank.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_cache_config.vh
shared memory optimization
2020-11-29 15:04:31 -08:00
VX_cache_core_req_bank_sel.v
L2 and L1 using different block size support, RTLsim fixes, dram_rsp_ready optimization
2020-11-21 09:47:56 -08:00
VX_cache_core_rsp_merge.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_cache_dram_req_arb.v
generic_register reset network optimization
2020-11-29 18:41:36 -08:00
VX_cache_miss_resrv.v
rename MSRQ to MSHR
2020-11-28 17:32:00 -05:00
VX_cache.v
shared memory optimization
2020-11-29 15:04:31 -08:00
VX_data_access.v
generic_register reset network optimization
2020-11-29 18:41:36 -08:00
VX_data_store.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_snp_forwarder.v
RAM blocks inference fixes
2020-11-30 14:02:47 -08:00
VX_snp_rsp_arb.v
generic_register reset network optimization
2020-11-29 18:41:36 -08:00
VX_tag_access.v
shared memory optimization
2020-11-29 15:04:31 -08:00
VX_tag_store.v
tabs cleanup
2020-11-28 17:08:01 -05:00
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