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8f451aa74cdf3b8416d2b8a5348bb7e8bdc27574
vortex/hw/rtl/cache
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Blaise Tine 04a1c0e9eb IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
2021-05-01 13:44:08 -07:00
..
VX_bank.v
IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
2021-05-01 13:44:08 -07:00
VX_cache_config.vh
code refactoring: DRAM => MEM renaming
2021-04-26 00:58:48 -07:00
VX_cache_core_req_bank_sel.v
perf counters generic size
2021-04-25 21:15:24 -07:00
VX_cache_core_rsp_merge.v
enabling 128-bit dram bus
2021-04-24 00:31:27 -04:00
VX_cache.v
IN_ORDER_MEM feature doesn't work becasue when cache bank's mem-req-queue is full, we need to schedule the mem response and skip the mshr
2021-05-01 13:44:08 -07:00
VX_data_access.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_flush_ctrl.v
minor update
2021-04-01 12:34:18 -07:00
VX_miss_resrv.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
VX_shared_mem.v
perf counters generic size
2021-04-25 21:15:24 -07:00
VX_tag_access.v
Merge branch 'master' of https://github.gatech.edu/casl/Vortex
2021-03-04 20:51:03 -08:00
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