d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
119 lines
3.5 KiB
Systemverilog
119 lines
3.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_mem_perf_if ();
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wire [`PERF_CTR_BITS-1:0] icache_reads;
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wire [`PERF_CTR_BITS-1:0] icache_read_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_reads;
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wire [`PERF_CTR_BITS-1:0] dcache_writes;
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wire [`PERF_CTR_BITS-1:0] dcache_read_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_write_misses;
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wire [`PERF_CTR_BITS-1:0] dcache_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] dcache_mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] smem_reads;
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wire [`PERF_CTR_BITS-1:0] smem_writes;
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wire [`PERF_CTR_BITS-1:0] smem_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] l2cache_reads;
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wire [`PERF_CTR_BITS-1:0] l2cache_writes;
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wire [`PERF_CTR_BITS-1:0] l2cache_read_misses;
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wire [`PERF_CTR_BITS-1:0] l2cache_write_misses;
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wire [`PERF_CTR_BITS-1:0] l2cache_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] l2cache_mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] l3cache_reads;
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wire [`PERF_CTR_BITS-1:0] l3cache_writes;
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wire [`PERF_CTR_BITS-1:0] l3cache_read_misses;
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wire [`PERF_CTR_BITS-1:0] l3cache_write_misses;
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wire [`PERF_CTR_BITS-1:0] l3cache_bank_stalls;
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wire [`PERF_CTR_BITS-1:0] l3cache_mshr_stalls;
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wire [`PERF_CTR_BITS-1:0] mem_reads;
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wire [`PERF_CTR_BITS-1:0] mem_writes;
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wire [`PERF_CTR_BITS-1:0] mem_latency;
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modport master (
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output icache_reads,
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output icache_read_misses,
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output dcache_reads,
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output dcache_writes,
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output dcache_read_misses,
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output dcache_write_misses,
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output dcache_bank_stalls,
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output dcache_mshr_stalls,
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output smem_reads,
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output smem_writes,
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output smem_bank_stalls,
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output l2cache_reads,
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output l2cache_writes,
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output l2cache_read_misses,
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output l2cache_write_misses,
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output l2cache_bank_stalls,
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output l2cache_mshr_stalls,
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output l3cache_reads,
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output l3cache_writes,
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output l3cache_read_misses,
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output l3cache_write_misses,
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output l3cache_bank_stalls,
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output l3cache_mshr_stalls,
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output mem_reads,
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output mem_writes,
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output mem_latency
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);
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modport slave (
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input icache_reads,
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input icache_read_misses,
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input dcache_reads,
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input dcache_writes,
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input dcache_read_misses,
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input dcache_write_misses,
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input dcache_bank_stalls,
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input dcache_mshr_stalls,
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input smem_reads,
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input smem_writes,
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input smem_bank_stalls,
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input l2cache_reads,
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input l2cache_writes,
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input l2cache_read_misses,
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input l2cache_write_misses,
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input l2cache_bank_stalls,
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input l2cache_mshr_stalls,
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input l3cache_reads,
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input l3cache_writes,
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input l3cache_read_misses,
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input l3cache_write_misses,
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input l3cache_bank_stalls,
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input l3cache_mshr_stalls,
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input mem_reads,
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input mem_writes,
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input mem_latency
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);
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endinterface
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