felsabbagh3 39516a6f98 Migrating fpga_synthesis_temp to main

2020-03-27 13:15:23 -07:00

..

quartus

synthesis fixes

2020-03-05 06:58:51 -05:00

VX_bank.v

fixed Modelsim build errors

2020-03-26 03:54:23 -04:00

VX_cache_config.v

MULTICORE WITH L2 WORKING

2020-03-09 01:17:11 -07:00

VX_cache_core_req_bank_sel.v

MULTICORE WITH L2 WORKING

2020-03-09 01:17:11 -07:00

VX_cache_dfq_queue.v

Cache Working on Mem Copy

2020-03-08 01:55:15 -08:00

VX_cache_dram_req_arb.v

MULTICORE WITH L2 WORKING

2020-03-09 01:17:11 -07:00

VX_cache_miss_resrv.v

Fixed most of the cache issues, mat_add left

2020-03-22 15:59:45 -07:00

VX_cache_req_queue.v

replace procedural continuous assignments and force MLAB inference for generic_queue_ll

2020-03-10 17:46:48 -04:00

VX_cache_wb_sel_merge.v

L3 and CLUSTRING WORKS

2020-03-10 02:41:47 -07:00

VX_cache.v

L3 and CLUSTRING WORKS

2020-03-10 02:41:47 -07:00

VX_dcache_llv_resp_bank_sel.v

Fixed all Cache Warnings

2020-03-07 14:34:05 -08:00

VX_fill_invalidator.v

Fix for Single-Threaded

2020-03-22 14:44:46 -07:00

VX_mrv_queue.v

Cache Working on Mem Copy

2020-03-08 01:55:15 -08:00

VX_snp_fwd_arb.v

fixed Modelsim build errors

2020-03-26 03:54:23 -04:00

VX_tag_data_access.v

Migrating fpga_synthesis_temp to main

2020-03-27 13:15:23 -07:00

VX_tag_data_structure.v

Migrating fpga_synthesis_temp to main

2020-03-27 13:15:23 -07:00