160 lines
4.2 KiB
Verilog
160 lines
4.2 KiB
Verilog
`timescale 1ns/1ps
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module VX_tb_divide();
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`ifdef TRACE
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initial
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begin
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$dumpfile("trace.vcd");
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$dumpvars(0,test);
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end
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`endif
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reg clk;
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reg rst;
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reg [31:0] numer, denom;
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wire [31:0] o_div[0:7], o_rem[0:7];
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genvar i;
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generate
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for (i = 0; i < 8; i++) begin : div_loop
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VX_divide#(
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.WIDTHN(32),
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.WIDTHD(32),
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.PIPELINE(i)
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) div(
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.clock(clk),
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.aclr(rst),
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.clken(1'b1),
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.numer(numer),
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.denom(denom),
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.quotient(o_div[i]),
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.remainder(o_rem[i])
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);
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end
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endgenerate
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initial begin
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clk = 0; rst = 0;
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numer = 56;
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denom = 11;
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$display("56 / 11 #0");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 1'bx || o_rem[1] != 1'bx) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #2");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1, EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 1'bx || o_rem[2] != 1'bx) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected x,x EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #4");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 5 || o_rem[2] != 1) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[3] != 1'bx || o_rem[3] != 1'bx) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected x,x EXITING");
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$finish();
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end
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#2;
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$display("56 / 11 #6");
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if (o_div[0] != 5 || o_rem[0] != 1) begin
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$display("PIPE0: div=", o_div[0], " rem=", o_rem[0]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[1] != 5 || o_rem[1] != 1) begin
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$display("PIPE1: div=", o_div[1], " rem=", o_rem[1]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[2] != 5 || o_rem[2] != 1) begin
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$display("PIPE2: div=", o_div[2], " rem=", o_rem[2]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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if (o_div[3] != 5 || o_rem[3] != 1) begin
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$display("PIPE3: div=", o_div[3], " rem=", o_rem[3]);
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$display("expected 5,1 EXITING");
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$finish();
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end
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$display("PASS");
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$finish();
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end
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always #1
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clk = !clk;
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endmodule: VX_tb_divide |