210 lines
8.3 KiB
Verilog
210 lines
8.3 KiB
Verilog
`include "VX_define.vh"
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module VX_lsu_unit #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_LSU_IO
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input wire clk,
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input wire reset,
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input wire no_slot_mem,
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VX_lsu_req_if lsu_req_if,
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// Write back to GPR
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VX_wb_if mem_wb_if,
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// Dcache interface
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VX_cache_core_req_if dcache_req_if,
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VX_cache_core_rsp_if dcache_rsp_if,
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output wire delay
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);
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VX_wb_if mem_wb_unqual_if();
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wire [`NUM_THREADS-1:0] use_valid;
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wire use_req_rw;
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wire [`NUM_THREADS-1:0][29:0] use_req_addr;
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wire [`NUM_THREADS-1:0][1:0] use_req_offset;
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wire [`NUM_THREADS-1:0][3:0] use_req_byteen;
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wire [`NUM_THREADS-1:0][31:0] use_req_data;
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wire [`BYTE_EN_BITS-1:0] use_mem_read;
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wire [4:0] use_rd;
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wire [`NW_BITS-1:0] use_warp_num;
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wire [1:0] use_wb;
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wire [31:0] use_pc;
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genvar i;
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// Generate Full Addresses
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wire[`NUM_THREADS-1:0][31:0] full_address;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset;
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end
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wire mem_req_rw = (lsu_req_if.mem_write != `BYTE_EN_NO);
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reg [3:0] wmask;
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always @(*) begin
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case ((mem_req_rw ? lsu_req_if.mem_write[1:0] : lsu_req_if.mem_read[1:0]))
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0: wmask = 4'b0001;
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1: wmask = 4'b0011;
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default : wmask = 4'b1111;
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endcase
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end
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wire [`NUM_THREADS-1:0][29:0] mem_req_addr;
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wire [`NUM_THREADS-1:0][1:0] mem_req_offset;
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wire [`NUM_THREADS-1:0][3:0] mem_req_byteen;
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wire [`NUM_THREADS-1:0][31:0] mem_req_data;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign mem_req_addr[i] = full_address[i][31:2];
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assign mem_req_offset[i] = full_address[i][1:0];
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assign mem_req_byteen[i] = wmask << full_address[i][1:0];
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assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0};
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end
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`IGNORE_WARNINGS_BEGIN
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wire[`NUM_THREADS-1:0][31:0] use_address;
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`IGNORE_WARNINGS_END
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VX_generic_register #(
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.N((`NUM_THREADS * 1) + (`NUM_THREADS * 32) + `BYTE_EN_BITS + 1 + (`NUM_THREADS * (30 + 2 + 4 + 32)) + 5 + `NW_BITS + 2 + 32)
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) lsu_buffer (
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.clk (clk),
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.reset (reset),
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.stall (delay),
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.flush (1'b0),
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.in ({lsu_req_if.valid, full_address, lsu_req_if.mem_read, mem_req_rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}),
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.out ({use_valid , use_address, use_mem_read , use_req_rw, use_req_addr, use_req_offset, use_req_byteen, use_req_data, use_rd , use_warp_num , use_wb , use_pc})
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);
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wire [`NUM_THREADS-1:0][1:0] mem_rsp_offset;
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wire [`BYTE_EN_BITS-1:0] core_rsp_mem_read;
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reg [`NUM_THREADS-1:0] mem_rsp_mask[`DCREQ_SIZE-1:0];
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wire [`LOG2UP(`DCREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr;
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wire mrq_full;
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wire mrq_push = (| dcache_req_if.valid) && dcache_req_if.ready
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&& (0 == use_req_rw); // only push read requests
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wire mrq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready;
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assign mrq_read_addr = dcache_rsp_if.tag[0][`LOG2UP(`DCREQ_SIZE)-1:0];
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wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.valid;
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wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd);
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VX_indexable_queue #(
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.DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 2) + `BYTE_EN_BITS + 5 + `NW_BITS),
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.SIZE (`DCREQ_SIZE)
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) mem_req_queue (
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.clk (clk),
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.reset (reset),
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.write_data ({mrq_write_addr, use_pc, use_wb, use_req_offset, use_mem_read, use_rd, use_warp_num}),
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.write_addr (mrq_write_addr),
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.push (mrq_push),
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.full (mrq_full),
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.pop (mrq_pop),
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.read_addr (mrq_read_addr),
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.read_data ({dbg_mrq_write_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num}),
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`UNUSED_PIN (empty)
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);
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always @(posedge clk) begin
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if (mrq_push) begin
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mem_rsp_mask[mrq_write_addr] <= use_valid;
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end
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if (mrq_pop_part) begin
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mem_rsp_mask[mrq_read_addr] <= mem_rsp_mask_upd;
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assert(($time < 2) || mrq_read_addr == dbg_mrq_write_addr);
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end
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end
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// Core Request
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assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}};
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assign dcache_req_if.rw = {`NUM_THREADS{use_req_rw}};
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assign dcache_req_if.byteen = use_req_byteen;
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assign dcache_req_if.addr = use_req_addr;
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assign dcache_req_if.data = use_req_data;
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`ifdef DBG_CORE_REQ_INFO
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assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr};
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`else
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assign dcache_req_if.tag = mrq_write_addr;
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`endif
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// Can't accept new request
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assign delay = mrq_full || !dcache_req_if.ready;
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// Core Response
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reg [`NUM_THREADS-1:0][31:0] core_rsp_data;
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wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted;
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for (i = 0; i < `NUM_THREADS; i++) begin
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assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0};
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always @(*) begin
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case (core_rsp_mem_read)
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`BYTE_EN_SB: core_rsp_data[i] = {{24{rsp_data_shifted[i][7]}}, rsp_data_shifted[i][7:0]};
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`BYTE_EN_SH: core_rsp_data[i] = {{16{rsp_data_shifted[i][15]}}, rsp_data_shifted[i][15:0]};
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`BYTE_EN_UB: core_rsp_data[i] = 32'(rsp_data_shifted[i][7:0]);
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`BYTE_EN_UH: core_rsp_data[i] = 32'(rsp_data_shifted[i][15:0]);
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default : core_rsp_data[i] = rsp_data_shifted[i];
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endcase
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end
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end
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assign mem_wb_unqual_if.valid = dcache_rsp_if.valid;
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assign mem_wb_unqual_if.data = core_rsp_data;
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// Can't accept new response
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assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if.valid));
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// From LSU to WB
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localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32;
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VX_generic_register #(.N(WB_REQ_SIZE)) lsu_to_wb (
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.clk (clk),
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.reset (reset),
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.stall (no_slot_mem),
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.flush (1'b0),
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.in ({mem_wb_unqual_if.valid, mem_wb_unqual_if.data, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.rd, mem_wb_unqual_if.wb, mem_wb_unqual_if.curr_PC}),
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.out ({mem_wb_if.valid, mem_wb_if.data, mem_wb_if.warp_num, mem_wb_if.rd, mem_wb_if.wb, mem_wb_if.curr_PC})
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);
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`SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid);
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`SCOPE_ASSIGN(scope_dcache_req_warp_num, use_warp_num);
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`SCOPE_ASSIGN(scope_dcache_req_curr_PC, use_pc);
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`SCOPE_ASSIGN(scope_dcache_req_addr, use_address);
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`SCOPE_ASSIGN(scope_dcache_req_rw, core_req_rw);
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`SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.byteen);
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`SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.data);
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`SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.tag);
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`SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.ready);
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`SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.valid);
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`SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.data);
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`SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.tag);
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`SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.ready);
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`ifdef DBG_PRINT_CORE_DCACHE
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always @(posedge clk) begin
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if ((| dcache_req_if.valid) && dcache_req_if.ready) begin
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$display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, rw=%0b, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h",
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$time, CORE_ID, use_valid, use_address, mrq_write_addr, use_req_rw, use_pc, use_rd, use_warp_num, use_req_byteen, use_req_data);
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end
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if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin
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$display("%t: D%0d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h",
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$time, CORE_ID, mem_wb_unqual_if.valid, mrq_read_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.data);
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end
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end
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`endif
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endmodule
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