Blaise Tine 7560202f8b cache bank refactoring - removing unecessary core response fifo & restoring single port data access

2021-02-21 21:47:46 -08:00

..

cache

lkg build rollout with 16cores optimization on arria10

2021-01-24 16:49:22 -08:00

core

lkg build rollout with 16cores optimization on arria10

2021-01-24 16:49:22 -08:00

pipeline

FPU float<->int conversion optimization

2020-12-29 15:37:45 -08:00

top1

minor update

2021-02-21 15:14:46 -08:00

top2

minor update

2021-02-21 15:14:46 -08:00

top4

minor update - registering execute units skid buffers

2021-02-21 15:11:08 -08:00

top8

minor update

2021-02-21 15:14:46 -08:00

top16

minor update

2021-02-21 15:14:46 -08:00

top32

minor update

2021-02-21 15:14:46 -08:00

top64

minor update

2021-02-21 15:14:46 -08:00

unittest

minor updates

2021-01-06 07:18:14 -08:00

vortex

Adding Altera Stratix 10 support

2020-12-27 10:44:57 -08:00

.gitignore

minor update

2021-02-21 15:14:46 -08:00

project.sdc

minor update

2021-02-15 09:23:40 -08:00

project.tcl

cache bank refactoring - removing unecessary core response fifo & restoring single port data access

2021-02-21 21:47:46 -08:00

timing-html.tcl

performance refactoring - rebalanced stream buffers accross the device to enforce output buffering rule at compoments boudaries, finally resolved block ram R/W collusion discrepencies,

2020-12-19 02:45:06 -08:00