Blaise Tine 3f5fd6d394 using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00

..

VX_bank.v

using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00

VX_cache_config.vh

cache request interfaces update

2021-02-10 20:55:04 -08:00

VX_cache_core_req_bank_sel.v

using 44-bit perf counters - aligned with DSP counters width

2021-02-28 02:05:47 -08:00

VX_cache_core_rsp_merge.v

using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00

VX_cache.v

using 44-bit perf counters - aligned with DSP counters width

2021-02-28 02:05:47 -08:00

VX_data_access.v

cache bank refactoring - removing unecessary core response fifo & restoring single port data access

2021-02-21 21:47:46 -08:00

VX_flush_ctrl.v

cache specialization for in-order DRAM reponses

2021-02-13 20:23:29 -08:00

VX_miss_resrv.v

cache specialization for in-order DRAM reponses

2021-02-13 20:23:29 -08:00

VX_shared_mem.v

using shiftreg-based skid buffers

2021-02-28 02:20:09 -08:00

VX_tag_access.v

cache specialization for in-order DRAM reponses

2021-02-13 20:23:29 -08:00