92 lines
3.6 KiB
Verilog
92 lines
3.6 KiB
Verilog
`include "VX_define.vh"
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module VX_writeback #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// inputs
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VX_commit_if alu_commit_if,
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VX_commit_if ld_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if fpu_commit_if,
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// outputs
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VX_writeback_if writeback_if
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);
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wire ld_valid = ld_commit_if.valid && ld_commit_if.wb;
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wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb;
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wire csr_valid = csr_commit_if.valid && csr_commit_if.wb;
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wire alu_valid = alu_commit_if.valid && alu_commit_if.wb;
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wire wb_valid;
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wire [`NW_BITS-1:0] wb_wid;
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wire [31:0] wb_PC;
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wire [`NUM_THREADS-1:0] wb_tmask;
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wire [`NR_BITS-1:0] wb_rd;
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wire [`NUM_THREADS-1:0][31:0] wb_data;
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wire wb_eop;
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assign wb_valid = ld_valid |
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fpu_valid |
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csr_valid |
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alu_valid;
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assign wb_wid = ld_valid ? ld_commit_if.wid :
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fpu_valid ? fpu_commit_if.wid :
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csr_valid ? csr_commit_if.wid :
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/*alu_valid ?*/ alu_commit_if.wid;
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assign wb_PC = ld_valid ? ld_commit_if.PC :
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fpu_valid ? fpu_commit_if.PC :
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csr_valid ? csr_commit_if.PC :
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/*alu_valid ?*/ alu_commit_if.PC;
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assign wb_tmask = ld_valid ? ld_commit_if.tmask :
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fpu_valid ? fpu_commit_if.tmask :
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csr_valid ? csr_commit_if.tmask :
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/*alu_valid ?*/ alu_commit_if.tmask;
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assign wb_rd = ld_valid ? ld_commit_if.rd :
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fpu_valid ? fpu_commit_if.rd :
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csr_valid ? csr_commit_if.rd :
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/*alu_valid ?*/ alu_commit_if.rd;
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assign wb_data = ld_valid ? ld_commit_if.data :
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fpu_valid ? fpu_commit_if.data :
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csr_valid ? csr_commit_if.data :
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/*alu_valid ?*/ alu_commit_if.data;
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assign wb_eop = ld_valid ? ld_commit_if.eop :
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fpu_valid ? fpu_commit_if.eop :
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csr_valid ? csr_commit_if.eop :
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/*alu_valid ?*/ alu_commit_if.eop;
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wire stall = ~writeback_if.ready && writeback_if.valid;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + 32 + `NUM_THREADS + `NR_BITS + (`NUM_THREADS * 32) + 1),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (!stall),
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.data_in ({wb_valid, wb_wid, wb_PC, wb_tmask, wb_rd, wb_data, wb_eop}),
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.data_out ({writeback_if.valid, writeback_if.wid, writeback_if.PC, writeback_if.tmask, writeback_if.rd, writeback_if.data, writeback_if.eop})
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);
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assign ld_commit_if.ready = !stall;
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assign fpu_commit_if.ready = !stall && !ld_valid;
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assign csr_commit_if.ready = !stall && !ld_valid && !fpu_valid;
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assign alu_commit_if.ready = !stall && !ld_valid && !fpu_valid && !csr_valid;
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// special workaround to get RISC-V tests Pass/Fail status
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reg [31:0] last_wb_value [`NUM_REGS-1:0] /* verilator public */;
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always @(posedge clk) begin
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if (writeback_if.valid && writeback_if.ready) begin
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last_wb_value[writeback_if.rd] <= writeback_if.data[0];
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end
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end
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endmodule |