38 lines
843 B
Systemverilog
38 lines
843 B
Systemverilog
`include "VX_tex_define.vh"
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module VX_tex_wrap #(
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parameter CORE_ID = 0
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) (
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input wire [`TEX_WRAP_BITS-1:0] wrap_i,
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input wire [31:0] coord_i,
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output wire [`FIXED_FRAC-1:0] coord_o
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);
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`UNUSED_PARAM (CORE_ID)
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reg [`FIXED_FRAC-1:0] coord_r;
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wire [`FIXED_FRAC-1:0] clamp;
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VX_tex_sat #(
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.IN_W (32),
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.OUT_W (`FIXED_FRAC)
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) sat_fx (
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.data_in (coord_i),
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.data_out (clamp)
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);
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always @(*) begin
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case (wrap_i)
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`TEX_WRAP_CLAMP:
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coord_r = clamp;
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`TEX_WRAP_MIRROR:
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coord_r = coord_i[`FIXED_FRAC-1:0] ^ {`FIXED_FRAC{coord_i[`FIXED_FRAC]}};
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default: //`TEX_WRAP_REPEAT
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coord_r = coord_i[`FIXED_FRAC-1:0];
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endcase
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end
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assign coord_o = coord_r;
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endmodule |