177 lines
5.4 KiB
Verilog
177 lines
5.4 KiB
Verilog
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`include "VX_define.v"
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module VX_d_e_reg (
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input wire clk,
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input wire[4:0] in_rd,
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input wire[4:0] in_rs1,
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input wire[4:0] in_rs2,
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input wire[31:0] in_a_reg_data[`NT_M1:0],
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input wire[31:0] in_b_reg_data[`NT_M1:0],
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input wire[4:0] in_alu_op,
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input wire[1:0] in_wb,
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input wire in_rs2_src, // NEW
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input wire[31:0] in_itype_immed, // new
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input wire[2:0] in_mem_read, // NEW
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input wire[2:0] in_mem_write,
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input wire[31:0] in_PC_next,
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input wire[2:0] in_branch_type,
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input wire in_fwd_stall,
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input wire in_branch_stall,
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input wire[19:0] in_upper_immed,
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input wire[11:0] in_csr_address, // done
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input wire in_is_csr, // done
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input wire[31:0] in_csr_mask, // done
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input wire[31:0] in_curr_PC,
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input wire in_jal,
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input wire[31:0] in_jal_offset,
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input wire in_freeze,
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input wire in_clone_stall,
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input wire in_valid[`NT_M1:0],
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input wire[`NW_M1:0] in_warp_num,
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output wire[11:0] out_csr_address, // done
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output wire out_is_csr, // done
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output wire[31:0] out_csr_mask, // done
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output wire[4:0] out_rd,
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output wire[4:0] out_rs1,
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output wire[4:0] out_rs2,
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output wire[31:0] out_a_reg_data[`NT_M1:0],
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output wire[31:0] out_b_reg_data[`NT_M1:0],
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output wire[4:0] out_alu_op,
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output wire[1:0] out_wb,
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output wire out_rs2_src, // NEW
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output wire[31:0] out_itype_immed, // new
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output wire[2:0] out_mem_read,
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output wire[2:0] out_mem_write,
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output wire[2:0] out_branch_type,
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output wire[19:0] out_upper_immed,
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output wire[31:0] out_curr_PC,
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output wire out_jal,
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output wire[31:0] out_jal_offset,
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output wire[31:0] out_PC_next,
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output wire out_valid[`NT_M1:0],
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output wire[`NW_M1:0] out_warp_num
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);
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reg[4:0] rd;
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reg[4:0] rs1;
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reg[4:0] rs2;
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reg[31:0] a_reg_data[`NT_M1:0];
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reg[31:0] b_reg_data[`NT_M1:0];
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reg[4:0] alu_op;
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reg[1:0] wb;
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reg[31:0] PC_next_out;
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reg rs2_src;
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reg[31:0] itype_immed;
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reg[2:0] mem_read;
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reg[2:0] mem_write;
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reg[2:0] branch_type;
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reg[19:0] upper_immed;
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reg[11:0] csr_address;
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reg is_csr;
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reg[31:0] csr_mask;
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reg[31:0] curr_PC;
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reg jal;
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reg[31:0] jal_offset;
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reg valid[`NT_M1:0];
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reg[31:0] reg_data_z[`NT_M1:0];
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reg valid_z[`NT_M1:0];
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reg[`NW_M1:0] warp_num;
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integer ini_reg;
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initial begin
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rd = 0;
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rs1 = 0;
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for (ini_reg = 0; ini_reg < `NT; ini_reg = ini_reg + 1)
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begin
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a_reg_data[ini_reg] = 0;
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b_reg_data[ini_reg] = 0;
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reg_data_z[ini_reg] = 0;
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valid[ini_reg] = 0;
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valid_z[ini_reg] = 0;
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end
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rs2 = 0;
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alu_op = 0;
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wb = `NO_WB;
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PC_next_out = 0;
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rs2_src = 0;
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itype_immed = 0;
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mem_read = `NO_MEM_READ;
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mem_write = `NO_MEM_WRITE;
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branch_type = `NO_BRANCH;
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upper_immed = 0;
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csr_address = 0;
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is_csr = 0;
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csr_mask = 0;
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curr_PC = 0;
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jal = `NO_JUMP;
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jal_offset = 0;
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warp_num = 0;
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end
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wire stalling;
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assign stalling = (in_fwd_stall == `STALL) || (in_branch_stall == `STALL) || (in_clone_stall == `STALL);
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assign out_rd = rd;
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assign out_rs1 = rs1;
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assign out_rs2 = rs2;
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assign out_a_reg_data = a_reg_data;
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assign out_b_reg_data = b_reg_data;
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assign out_alu_op = alu_op;
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assign out_wb = wb;
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assign out_PC_next = PC_next_out;
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assign out_rs2_src = rs2_src;
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assign out_itype_immed = itype_immed;
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assign out_mem_read = mem_read;
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assign out_mem_write = mem_write;
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assign out_branch_type = branch_type;
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assign out_upper_immed = upper_immed;
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assign out_csr_address = csr_address;
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assign out_is_csr = is_csr;
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assign out_csr_mask = csr_mask;
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assign out_jal = jal;
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assign out_jal_offset = jal_offset;
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assign out_curr_PC = curr_PC;
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assign out_valid = valid;
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assign out_warp_num = warp_num;
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always @(posedge clk) begin
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if (in_freeze == 1'h0) begin
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rd <= stalling ? 5'h0 : in_rd;
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rs1 <= stalling ? 5'h0 : in_rs1;
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rs2 <= stalling ? 5'h0 : in_rs2;
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a_reg_data <= stalling ? reg_data_z : in_a_reg_data;
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b_reg_data <= stalling ? reg_data_z : in_b_reg_data;
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alu_op <= stalling ? `NO_ALU : in_alu_op;
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wb <= stalling ? `NO_WB : in_wb;
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PC_next_out <= stalling ? 32'h0 : in_PC_next;
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rs2_src <= stalling ? `RS2_REG : in_rs2_src;
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itype_immed <= stalling ? 32'hdeadbeef : in_itype_immed;
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mem_read <= stalling ? `NO_MEM_READ : in_mem_read;
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mem_write <= stalling ? `NO_MEM_WRITE: in_mem_write;
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branch_type <= stalling ? `NO_BRANCH : in_branch_type;
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upper_immed <= stalling ? 20'h0 : in_upper_immed;
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csr_address <= stalling ? 12'h0 : in_csr_address;
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is_csr <= stalling ? 1'h0 : in_is_csr;
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csr_mask <= stalling ? 32'h0 : in_csr_mask;
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jal <= stalling ? `NO_JUMP : in_jal;
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jal_offset <= stalling ? 32'h0 : in_jal_offset;
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curr_PC <= stalling ? 32'h0 : in_curr_PC;
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valid <= stalling ? valid_z : in_valid;
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warp_num <= stalling ? 0 : in_warp_num;
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end
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end
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endmodule
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