100 lines
2.4 KiB
Verilog
100 lines
2.4 KiB
Verilog
`include "VX_define.vh"
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// control module to support multi-cycle read for fp register
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module VX_gpr_fp_ctrl (
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input wire clk,
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input wire reset,
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input wire [`NUM_THREADS-1:0][31:0] rs1_int_data,
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input wire [`NUM_THREADS-1:0][31:0] rs2_int_data,
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input wire [`NUM_THREADS-1:0][31:0] rs1_fp_data,
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input wire [`NUM_THREADS-1:0][31:0] rs2_fp_data,
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// outputs
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output wire [`NR_BITS-1:0] raddr1,
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output wire [`NR_BITS-1:0] raddr2,
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VX_gpr_read_if gpr_read_if
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);
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// param
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localparam GPR_DELAY_WID = 1;
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reg [GPR_DELAY_WID-1:0] multi_cyc_state;
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reg [`NUM_THREADS-1:0][31:0] tmp_rs1_data;
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reg [`NUM_THREADS-1:0][31:0] tmp_rs2_data;
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reg [`NUM_THREADS-1:0][31:0] rs1_data;
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reg [`NUM_THREADS-1:0][31:0] rs2_data;
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reg [`NUM_THREADS-1:0][31:0] rs3_data;
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wire gpr_delay;
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wire gpr_fire = gpr_read_if.valid && gpr_read_if.ready;
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always @(posedge clk) begin
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if (reset) begin
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multi_cyc_state <= 0;
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end else if (gpr_delay) begin
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multi_cyc_state <= 1;
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end else if (gpr_fire) begin
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multi_cyc_state <= 0;
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end
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end
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// select rs1 data
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always @(posedge clk) begin
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if (reset) begin
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tmp_rs1_data <= 0;
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end else begin
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if (gpr_delay) begin
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if (gpr_read_if.rs1_is_fp) begin
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tmp_rs1_data <= rs1_fp_data;
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end else begin
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tmp_rs1_data <= rs1_int_data;
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end
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end
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end
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end
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// select rs2 data
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always @(posedge clk) begin
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if(reset) begin
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tmp_rs2_data <= 0;
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end else begin
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if (gpr_delay) begin
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if (gpr_read_if.rs2_is_fp) begin
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tmp_rs2_data <= rs2_fp_data;
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end else begin
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tmp_rs2_data <= rs2_int_data;
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end
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end
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end
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end
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// outputs
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assign gpr_delay = gpr_read_if.valid && gpr_read_if.use_rs3 && (0 == multi_cyc_state);
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assign raddr1 = multi_cyc_state ? gpr_read_if.rs3 : gpr_read_if.rs1;
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assign raddr2 = gpr_read_if.rs2;
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always @(*) begin
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if (gpr_read_if.use_rs3) begin
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rs1_data = tmp_rs1_data;
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rs2_data = tmp_rs2_data;
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rs3_data = rs1_fp_data;
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end else begin
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rs1_data = gpr_read_if.rs1_is_fp ? rs1_fp_data : rs1_int_data;
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rs2_data = gpr_read_if.rs2_is_fp ? rs2_fp_data : rs2_int_data;
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rs3_data = {`NUM_THREADS{32'h8000_0000}}; // default value: -0 in single fp
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end
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end
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assign gpr_read_if.ready = ~gpr_delay;
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assign gpr_read_if.rs1_data = rs1_data;
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assign gpr_read_if.rs2_data = rs2_data;
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assign gpr_read_if.rs3_data = rs3_data;
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endmodule |