15 lines
212 B
Verilog
15 lines
212 B
Verilog
`ifndef VX_ICACHE_RSP
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`define VX_ICACHE_RSP
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`include "../VX_define.vh"
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interface VX_icache_response_inter ();
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// wire ready;
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// wire stall;
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wire [31:0] instruction;
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wire delay;
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endinterface
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`endif |