d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
130 lines
3.3 KiB
Systemverilog
130 lines
3.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_priority_encoder #(
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parameter N = 1,
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parameter REVERSE = 0,
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parameter MODEL = 1,
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parameter LN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [N-1:0] onehot,
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output wire [LN-1:0] index,
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output wire valid_out
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);
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wire [N-1:0] reversed;
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if (REVERSE != 0) begin
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for (genvar i = 0; i < N; ++i) begin
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assign reversed[N-i-1] = data_in[i];
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end
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end else begin
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assign reversed = data_in;
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end
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if (N == 1) begin
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assign onehot = reversed;
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assign index = '0;
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assign valid_out = reversed;
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end else if (N == 2) begin
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assign onehot = {~reversed[0], reversed[0]};
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assign index = ~reversed[0];
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assign valid_out = (| reversed);
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end else if (MODEL == 1) begin
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wire [N-1:0] scan_lo;
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VX_scan #(
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.N (N),
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.OP (2)
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) scan (
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.data_in (reversed),
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.data_out (scan_lo)
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);
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VX_lzc #(
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.N (N),
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.REVERSE (1)
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) lzc (
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.data_in (reversed),
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.data_out (index),
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`UNUSED_PIN (valid_out)
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);
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assign onehot = scan_lo & {(~scan_lo[N-2:0]), 1'b1};
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assign valid_out = scan_lo[N-1];
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end else if (MODEL == 2) begin
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`IGNORE_WARNINGS_BEGIN
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wire [N-1:0] higher_pri_regs;
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`IGNORE_WARNINGS_END
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assign higher_pri_regs[N-1:1] = higher_pri_regs[N-2:0] | reversed[N-2:0];
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assign higher_pri_regs[0] = 1'b0;
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assign onehot[N-1:0] = reversed[N-1:0] & ~higher_pri_regs[N-1:0];
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VX_lzc #(
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.N (N),
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.REVERSE (1)
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) lzc (
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.data_in (reversed),
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.data_out (index),
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.valid_out (valid_out)
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);
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end else if (MODEL == 3) begin
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assign onehot = reversed & -reversed;
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VX_lzc #(
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.N (N),
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.REVERSE (1)
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) lzc (
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.data_in (reversed),
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.data_out (index),
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.valid_out (valid_out)
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);
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end else begin
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reg [LN-1:0] index_r;
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reg [N-1:0] onehot_r;
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always @(*) begin
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index_r = 'x;
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onehot_r = 'x;
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for (integer i = N-1; i >= 0; --i) begin
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if (reversed[i]) begin
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index_r = LN'(i);
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onehot_r = '0;
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onehot_r[i] = 1'b1;
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end
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end
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end
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assign index = index_r;
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assign onehot = onehot_r;
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assign valid_out = (| reversed);
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end
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endmodule
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`TRACING_ON
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