93 lines
2.3 KiB
Systemverilog
93 lines
2.3 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_lzc #(
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parameter N = 2,
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parameter REVERSE = 0, // 0 -> leading zero, 1 -> trailing zero,
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parameter LOGN = `LOG2UP(N)
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) (
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input wire [N-1:0] data_in,
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output wire [LOGN-1:0] data_out,
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output logic valid_out
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);
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if (N == 1) begin
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`UNUSED_PARAM (REVERSE)
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assign data_out = '0;
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assign valid_out = data_in;
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end else begin
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wire [N-1:0][LOGN-1:0] indices;
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for (genvar i = 0; i < N; ++i) begin
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assign indices[i] = REVERSE ? LOGN'(i) : LOGN'(N-1-i);
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end
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VX_find_first #(
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.N (N),
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.DATAW (LOGN),
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.REVERSE (!REVERSE)
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) find_first (
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.data_in (indices),
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.valid_in (data_in),
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.data_out (data_out),
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.valid_out (valid_out)
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);
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end
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endmodule
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module VX_lzc_rr #(
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parameter N = 2
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) (
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input wire clk,
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input wire reset,
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input wire [N-1:0] data_in,
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output logic [$clog2(N)-1:0] data_out,
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output logic valid_out
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);
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logic [$clog2(N)-1:0] current_idx;
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always @(*) begin
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integer i;
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data_out = 0;
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for (i = 0; i < N; i += 1) begin
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if (data_in[(current_idx + i) % N] == 1'b1) begin
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data_out = (current_idx + i) % N;
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break;
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end
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end
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end
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assign valid_out = |data_in;
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always @(posedge clk) begin
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if (reset) begin
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current_idx <= 0;
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end else begin
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if (valid_out) begin
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current_idx <= (current_idx + 1) % N;
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end
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end
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end
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endmodule
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`TRACING_ON
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