d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
58 lines
1.8 KiB
Systemverilog
58 lines
1.8 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_platform.vh"
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`TRACING_OFF
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module VX_find_first #(
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parameter N = 1,
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parameter DATAW = 1,
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parameter REVERSE = 0
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) (
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input wire [N-1:0][DATAW-1:0] data_in,
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input wire [N-1:0] valid_in,
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output wire [DATAW-1:0] data_out,
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output wire valid_out
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);
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localparam LOGN = `CLOG2(N);
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localparam TL = (1 << LOGN) - 1;
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localparam TN = (1 << (LOGN+1)) - 1;
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`IGNORE_WARNINGS_BEGIN
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wire [TN-1:0] s_n;
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wire [TN-1:0][DATAW-1:0] d_n;
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`IGNORE_WARNINGS_END
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for (genvar i = 0; i < N; ++i) begin
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assign s_n[TL+i] = REVERSE ? valid_in[N-1-i] : valid_in[i];
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assign d_n[TL+i] = REVERSE ? data_in[N-1-i] : data_in[i];
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end
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for (genvar i = TL+N; i < TN; ++i) begin
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assign s_n[i] = 0;
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assign d_n[i] = '0;
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end
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for (genvar j = 0; j < LOGN; ++j) begin
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for (genvar i = 0; i < (2**j); ++i) begin
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assign s_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] | s_n[2**(j+1)-1+i*2+1];
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assign d_n[2**j-1+i] = s_n[2**(j+1)-1+i*2] ? d_n[2**(j+1)-1+i*2] : d_n[2**(j+1)-1+i*2+1];
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end
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end
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assign valid_out = s_n[0];
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assign data_out = d_n[0];
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endmodule
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`TRACING_ON
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