223 lines
8.0 KiB
Verilog
223 lines
8.0 KiB
Verilog
`include "VX_platform.vh"
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`include "VX_define.vh"
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module VX_tex_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// Texture unit <-> Memory Unit
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VX_dcache_core_req_if dcache_req_if,
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VX_dcache_core_rsp_if dcache_rsp_if,
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// Inputs
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VX_tex_req_if tex_req_if,
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VX_tex_csr_if tex_csr_if,
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// Outputs
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VX_tex_rsp_if tex_rsp_if
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);
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localparam MEM_REQ_TAGW = `NW_BITS + 32 + 1 + `NR_BITS + `NTEX_BITS;
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`UNUSED_PARAM (CORE_ID)
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`UNUSED_VAR (reset)
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wire rsp_valid;
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wire [`NW_BITS-1:0] rsp_wid;
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wire [`NUM_THREADS-1:0] rsp_tmask;
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wire [31:0] rsp_PC;
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wire [`NR_BITS-1:0] rsp_rd;
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wire rsp_wb;
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wire [`NUM_THREADS-1:0][31:0] rsp_data;
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wire stall_in, stall_out;
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reg [`TEX_ADDR_BITS-1:0] tex_addr [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_FMT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_WIDTH_BITS-1:0] tex_width [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_HEIGHT_BITS-1:0] tex_height [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_STRIDE_BITS-1:0] tex_stride [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_WRAP_BITS-1:0] tex_wrap_u [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_WRAP_BITS-1:0] tex_wrap_v [`NUM_TEX_UNITS-1: 0];
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reg [`TEX_FILTER_BITS-1:0] tex_filter [`NUM_TEX_UNITS-1: 0];
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// CSRs programming
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for (genvar i = 0; i < `NUM_TEX_UNITS; ++i) begin
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always @(posedge clk ) begin
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if (reset) begin
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tex_addr[i] <= 0;
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tex_format[i] <= 0;
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tex_width[i] <= 0;
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tex_height[i] <= 0;
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tex_stride[i] <= 0;
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tex_wrap_u[i] <= 0;
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tex_wrap_v[i] <= 0;
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tex_filter[i] <= 0;
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end begin
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if (tex_csr_if.write_enable) begin
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case (tex_csr_if.write_addr)
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`CSR_TEX_ADDR(i) : tex_addr[i] <= tex_csr_if.write_data;
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`CSR_TEX_FORMAT(i) : tex_format[i] <= tex_csr_if.write_data;
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`CSR_TEX_WIDTH(i) : tex_width[i] <= tex_csr_if.write_data;
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`CSR_TEX_HEIGHT(i) : tex_height[i] <= tex_csr_if.write_data;
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`CSR_TEX_STRIDE(i) : tex_stride[i] <= tex_csr_if.write_data;
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`CSR_TEX_WRAP_U(i) : tex_wrap_u[i] <= tex_csr_if.write_data;
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`CSR_TEX_WRAP_V(i) : tex_wrap_v[i] <= tex_csr_if.write_data;
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`CSR_TEX_FILTER(i) : tex_filter[i] <= tex_csr_if.write_data;
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default:
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assert(tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0)
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&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES));
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endcase
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end
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end
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end
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end
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// address generation
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wire [3:0] mem_req_valid;
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wire [3:0][31:0] mem_req_addr;
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wire [TAG_IN_WIDTH-1:0] mem_req_tag;
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wire mem_req_ready;
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wire mem_rsp_valid;
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wire [3:0][31:0] mem_rsp_data;
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wire [TAG_IN_WIDTH-1:0] mem_rsp_tag;
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wire mem_rsp_ready;
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VX_tex_addr_gen #(
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.FRAC_BITS(20)
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) tex_addr_gen (
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.clk (clk),
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.reset (reset),
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.valid_in (tex_req_if.valid),
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.ready_in (tex_req_if.ready),
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.req_tag ({tex_req_if.wid, tex_req_if.PC, tex_req_if.rd, tex_req_if.wb}),
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.filter (tex_filter[tex_req_if.unit]),
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.wrap_u (tex_wrap_ufilter[tex_req_if.unit]),
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.wrap_v (tex_wrap_v[tex_req_if.unit]),
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.base_addr (tex_addr[tex_req_if.unit]),
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.log2_stride (tex_stride[tex_req_if.unit]),
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.log2_width (tex_width[tex_req_if.unit]),
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.log2_height (tex_height[tex_req_if.unit]),
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.coord_u (tex_req_if.u),
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.coord_v (tex_req_if.v),
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.lod (tex_req_if.lod),
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.mem_req_valid (mem_req_valid),
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.mem_req_tag (mem_req_tag),
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.mem_req_addr (mem_req_addr),
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.mem_req_ready (mem_req_ready)
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);
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// retrieve texel values from memory
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VX_tex_memory #(
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.CORE_ID (CORE_ID),
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.REQ_TAG_WIDTH (MEM_REQ_TAGW)
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) tex_memory (
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.clk (clk),
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.reset (reset),
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// memory interface
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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// inputs
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req_valid (mem_req_valid),
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req_addr (mem_req_addr),
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req_tag (mem_req_tag),
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req_ready (mem_req_ready),
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// outputs
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rsp_valid (mem_rsp_valid),
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rsp_texel (mem_rsp_data),
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rsp_tag (mem_rsp_tag),
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rsp_ready (mem_rsp_ready)
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);
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// apply sampler
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VX_tex_sampler #(
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.CORE_ID (CORE_ID)
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) tex_sampler (
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.clk (clk),
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.reset (reset)
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// inputs
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//.valid_in (mem_rsp_valid),
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//.texel (mem_rsp_data),
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//.req_wid (mem_rsp_tag),
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//.req_PC (mem_rsp_tag),
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//.format (mem_rsp_tag),
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//.ready_in (mem_rsp_ready),
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);
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assign tex_req_if.ready = (& pt_addr_ready);
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assign lsu_req_if.valid = (& pt_addr_valid);
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assign lsu_req_if.wid = tex_req_if.wid;
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assign lsu_req_if.tmask = tex_req_if.tmask;
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assign lsu_req_if.PC = tex_req_if.PC;
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assign lsu_req_if.rd = tex_req_if.rd;
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assign lsu_req_if.wb = tex_req_if.wb;
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assign lsu_req_if.offset = 32'h0000;
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assign lsu_req_if.op_type = `OP_BITS'({1'b0, 3'b000}); //func3 for word load??
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assign lsu_req_if.store_data = {`NUM_THREADS{32'h0000}};
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// wait buffer for fragments / replace with cache/state fragment fifo for bilerp
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// no filtering for point sampling -> directly from dcache to output response
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assign rsp_valid = ld_commit_if.valid;
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assign rsp_wid = ld_commit_if.wid;
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assign rsp_tmask = ld_commit_if.tmask;
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assign rsp_PC = ld_commit_if.PC;
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assign rsp_rd = ld_commit_if.rd;
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assign rsp_wb = ld_commit_if.wb;
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assign rsp_data = ld_commit_if.data;
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VX_pipe_register #(
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.DATAW (1 + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + 1 + (`NUM_THREADS * 32)),
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.RESETW (1)
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) pipe_reg (
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.clk (clk),
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.reset (reset),
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.enable (~stall_out),
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.data_in ({rsp_valid, rsp_wid, rsp_tmask, rsp_PC, rsp_rd, rsp_wb, rsp_data}),
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.data_out ({tex_rsp_if.valid, tex_rsp_if.wid, tex_rsp_if.tmask, tex_rsp_if.PC, tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.data})
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);
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// output
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assign stall_out = ~tex_rsp_if.ready && tex_rsp_if.valid;
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// can accept new request?
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assign stall_in = stall_out;
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assign ld_commit_if.ready = ~stall_in;
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`ifdef DBG_PRINT_TEX
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always @(posedge clk) begin
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if (tex_csr_if.write_enable
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&& (tex_csr_if.write_addr >= `CSR_TEX_BEGIN(0)
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&& tex_csr_if.write_addr < `CSR_TEX_BEGIN(`CSR_TEX_STATES))) begin
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$display("%t: core%0d-tex_csr: csr_tex0_addr, csr_data=%0h", $time, CORE_ID, tex_addr[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_format, csr_data=%0h", $time, CORE_ID, tex_format[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_width, csr_data=%0h", $time, CORE_ID, tex_width[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_height, csr_data=%0h", $time, CORE_ID, tex_height[0]);
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$display("%t: core%0d-tex_csr: CSR_TEX0_PITCH, csr_data=%0h", $time, CORE_ID, tex_stride[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_u, csr_data=%0h", $time, CORE_ID, tex_wrap_u[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_wrap_v, csr_data=%0h", $time, CORE_ID, tex_wrap_v[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_min_filter, csr_data=%0h", $time, CORE_ID, tex_min_filter[0]);
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$display("%t: core%0d-tex_csr: csr_tex0_max_filter, csr_data=%0h", $time, CORE_ID, tex_max_filter[0]);
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end
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end
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`endif
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endmodule |