18 lines
387 B
Verilog
18 lines
387 B
Verilog
`ifndef VX_PERF_PIPELINE_IF
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`define VX_PERF_PIPELINE_IF
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`include "VX_define.vh"
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interface VX_perf_pipeline_if ();
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wire [43:0] ibf_stalls;
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wire [43:0] scb_stalls;
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wire [43:0] lsu_stalls;
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wire [43:0] csr_stalls;
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wire [43:0] alu_stalls;
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wire [43:0] gpu_stalls;
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`ifdef EXT_F_ENABLE
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wire [43:0] fpu_stalls;
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`endif
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endinterface
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`endif |