17 lines
244 B
Verilog
17 lines
244 B
Verilog
`ifndef VX_CSR_IO_REQ_IF
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`define VX_CSR_IO_REQ_IF
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`include "VX_define.vh"
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interface VX_csr_io_req_if ();
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wire valid;
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wire rw;
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wire [11:0] addr;
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wire [31:0] data;
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wire ready;
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endinterface
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`endif
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