223 lines
8.0 KiB
Verilog
223 lines
8.0 KiB
Verilog
`include "VX_define.vh"
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module VX_pipeline #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_ISTAGE_IO
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_PIPELINE_IO
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`SCOPE_SIGNALS_BE_IO
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// Clock
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input wire clk,
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input wire reset,
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// Dcache core request
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output wire [`NUM_THREADS-1:0] dcache_req_valid,
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output wire [`NUM_THREADS-1:0] dcache_req_rw,
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output wire [`NUM_THREADS-1:0][3:0] dcache_req_byteen,
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output wire [`NUM_THREADS-1:0][29:0] dcache_req_addr,
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output wire [`NUM_THREADS-1:0][31:0] dcache_req_data,
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output wire [`DCORE_TAG_WIDTH-1:0] dcache_req_tag,
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input wire dcache_req_ready,
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// Dcache core reponse
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input wire [`NUM_THREADS-1:0] dcache_rsp_valid,
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input wire [`NUM_THREADS-1:0][31:0] dcache_rsp_data,
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input wire [`DCORE_TAG_WIDTH-1:0] dcache_rsp_tag,
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output wire dcache_rsp_ready,
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// Icache core request
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output wire icache_req_valid,
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output wire icache_req_rw,
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output wire [3:0] icache_req_byteen,
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output wire [29:0] icache_req_addr,
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output wire [31:0] icache_req_data,
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output wire [`ICORE_TAG_WIDTH-1:0] icache_req_tag,
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input wire icache_req_ready,
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// Icache core response
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input wire icache_rsp_valid,
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input wire [31:0] icache_rsp_data,
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input wire [`ICORE_TAG_WIDTH-1:0] icache_rsp_tag,
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output wire icache_rsp_ready,
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// CSR I/O Request
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input wire csr_io_req_valid,
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input wire[11:0] csr_io_req_addr,
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input wire csr_io_req_rw,
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input wire[31:0] csr_io_req_data,
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output wire csr_io_req_ready,
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// CSR I/O Response
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output wire csr_io_rsp_valid,
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output wire[31:0] csr_io_rsp_data,
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input wire csr_io_rsp_ready,
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// Status
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output wire busy,
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output wire ebreak
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);
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`DEBUG_BEGIN
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wire scheduler_empty;
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`DEBUG_END
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wire memory_delay;
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wire exec_delay;
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wire gpr_stage_delay;
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wire schedule_delay;
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// Dcache
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VX_cache_core_req_if #(
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.NUM_REQUESTS(`NUM_THREADS),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_dcache_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(`NUM_THREADS),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`DCORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS)
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) core_dcache_rsp_if();
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// Icache
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VX_cache_core_req_if #(
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.NUM_REQUESTS(1),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
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) core_icache_req_if();
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VX_cache_core_rsp_if #(
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.NUM_REQUESTS(1),
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.WORD_SIZE(4),
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.CORE_TAG_WIDTH(`ICORE_TAG_WIDTH),
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.CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS)
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) core_icache_rsp_if();
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// CSR I/O
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VX_csr_io_req_if csr_io_req_if();
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assign csr_io_req_if.valid = csr_io_req_valid;
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assign csr_io_req_if.rw = csr_io_req_rw;
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assign csr_io_req_if.addr = csr_io_req_addr;
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assign csr_io_req_if.data = csr_io_req_data;
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assign csr_io_req_ready = csr_io_req_if.ready;
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VX_csr_io_rsp_if csr_io_rsp_if();
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assign csr_io_rsp_valid = csr_io_rsp_if.valid;
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assign csr_io_rsp_data = csr_io_rsp_if.data;
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assign csr_io_rsp_if.ready = csr_io_rsp_ready;
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// Front-end to Back-end
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VX_backend_req_if bckE_req_if();
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// Back-end to Front-end
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VX_wb_if writeback_if();
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VX_branch_rsp_if branch_rsp_if();
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VX_jal_rsp_if jal_rsp_if();
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// Warp controls
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VX_warp_ctl_if warp_ctl_if();
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VX_front_end #(
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.CORE_ID(CORE_ID)
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) front_end (
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`SCOPE_SIGNALS_ISTAGE_BIND
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.clk (clk),
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.reset (reset),
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.warp_ctl_if (warp_ctl_if),
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.bckE_req_if (bckE_req_if),
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.schedule_delay (schedule_delay),
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.icache_rsp_if (core_icache_rsp_if),
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.icache_req_if (core_icache_req_if),
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.jal_rsp_if (jal_rsp_if),
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.branch_rsp_if (branch_rsp_if),
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.busy (busy)
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);
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VX_scheduler scheduler (
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.clk (clk),
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.reset (reset),
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.memory_delay (memory_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay(gpr_stage_delay),
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.bckE_req_if (bckE_req_if),
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.writeback_if (writeback_if),
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.schedule_delay (schedule_delay),
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.is_empty (scheduler_empty)
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);
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VX_back_end #(
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.CORE_ID(CORE_ID)
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) back_end (
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`SCOPE_SIGNALS_LSU_BIND
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`SCOPE_SIGNALS_BE_BIND
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.clk (clk),
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.reset (reset),
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.csr_io_req_if (csr_io_req_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.schedule_delay (schedule_delay),
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.warp_ctl_if (warp_ctl_if),
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.bckE_req_if (bckE_req_if),
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.jal_rsp_if (jal_rsp_if),
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.branch_rsp_if (branch_rsp_if),
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.dcache_req_if (core_dcache_req_if),
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.dcache_rsp_if (core_dcache_rsp_if),
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.writeback_if (writeback_if),
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.mem_delay (memory_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay),
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.ebreak (ebreak)
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);
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assign dcache_req_valid = core_dcache_req_if.core_req_valid;
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assign dcache_req_rw = core_dcache_req_if.core_req_rw;
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assign dcache_req_byteen = core_dcache_req_if.core_req_byteen;
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assign dcache_req_addr = core_dcache_req_if.core_req_addr;
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assign dcache_req_data = core_dcache_req_if.core_req_data;
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assign dcache_req_tag = core_dcache_req_if.core_req_tag;
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assign core_dcache_req_if.core_req_ready = dcache_req_ready;
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assign core_dcache_rsp_if.core_rsp_valid = dcache_rsp_valid;
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assign core_dcache_rsp_if.core_rsp_data = dcache_rsp_data;
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assign core_dcache_rsp_if.core_rsp_tag = dcache_rsp_tag;
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assign dcache_rsp_ready = core_dcache_rsp_if.core_rsp_ready;
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assign icache_req_valid = core_icache_req_if.core_req_valid;
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assign icache_req_rw = core_icache_req_if.core_req_rw;
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assign icache_req_byteen = core_icache_req_if.core_req_byteen;
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assign icache_req_addr = core_icache_req_if.core_req_addr;
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assign icache_req_data = core_icache_req_if.core_req_data;
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assign icache_req_tag = core_icache_req_if.core_req_tag;
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assign core_icache_req_if.core_req_ready = icache_req_ready;
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assign core_icache_rsp_if.core_rsp_valid = icache_rsp_valid;
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assign core_icache_rsp_if.core_rsp_data = icache_rsp_data;
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assign core_icache_rsp_if.core_rsp_tag = icache_rsp_tag;
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assign icache_rsp_ready = core_icache_rsp_if.core_rsp_ready;
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`SCOPE_ASSIGN(scope_busy, busy);
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`SCOPE_ASSIGN(scope_schedule_delay, schedule_delay);
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`SCOPE_ASSIGN(scope_memory_delay, memory_delay);
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`SCOPE_ASSIGN(scope_exec_delay, exec_delay);
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`SCOPE_ASSIGN(scope_gpr_stage_delay, gpr_stage_delay);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if ((| writeback_if.valid) && (writeback_if.wb != 0)) begin
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$display("%t: Core%0d-WB: warp=%0d, rd=%0d, data=%0h", $time, CORE_ID, writeback_if.warp_num, writeback_if.rd, writeback_if.data);
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end
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if (schedule_delay || memory_delay || exec_delay || gpr_stage_delay) begin
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$display("%t: Core%0d-Delay: sched=%b, mem=%b, exec=%b, gpr=%b ", $time, CORE_ID, schedule_delay, memory_delay, exec_delay, gpr_stage_delay);
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end
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end
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`endif
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endmodule
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