86 lines
3.1 KiB
Verilog
86 lines
3.1 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_io_arb #(
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parameter NUM_REQUESTS = 1,
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parameter REQS_BITS = `CLOG2(NUM_REQUESTS)
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) (
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input wire clk,
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input wire reset,
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input wire [REQS_BITS-1:0] request_id,
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// input requests
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input wire in_csr_io_req_valid,
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input wire [11:0] in_csr_io_req_addr,
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input wire in_csr_io_req_rw,
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input wire [31:0] in_csr_io_req_data,
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output wire in_csr_io_req_ready,
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// input response
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input wire [NUM_REQUESTS-1:0] in_csr_io_rsp_valid,
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input wire [NUM_REQUESTS-1:0][31:0] in_csr_io_rsp_data,
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output wire [NUM_REQUESTS-1:0] in_csr_io_rsp_ready,
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// output request
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output wire [NUM_REQUESTS-1:0] out_csr_io_req_valid,
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output wire [NUM_REQUESTS-1:0][11:0] out_csr_io_req_addr,
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output wire [NUM_REQUESTS-1:0] out_csr_io_req_rw,
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output wire [NUM_REQUESTS-1:0][31:0] out_csr_io_req_data,
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input wire [NUM_REQUESTS-1:0] out_csr_io_req_ready,
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// output response
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output wire out_csr_io_rsp_valid,
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output wire [31:0] out_csr_io_rsp_data,
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input wire out_csr_io_rsp_ready
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);
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if (NUM_REQUESTS == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign out_csr_io_req_valid = in_csr_io_req_valid;
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assign out_csr_io_req_rw = in_csr_io_req_rw;
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assign out_csr_io_req_addr = in_csr_io_req_addr;
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assign out_csr_io_req_data = in_csr_io_req_data;
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assign in_csr_io_req_ready = out_csr_io_req_ready;
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assign out_csr_io_rsp_valid = in_csr_io_rsp_valid;
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assign out_csr_io_rsp_data = in_csr_io_rsp_data;
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assign in_csr_io_rsp_ready = out_csr_io_rsp_ready;
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end else begin
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genvar i;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign out_csr_io_req_valid[i] = in_csr_io_req_valid && (request_id == `REQS_BITS'(i));
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assign out_csr_io_req_rw[i] = in_csr_io_req_rw;
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assign out_csr_io_req_addr[i] = in_csr_io_req_addr;
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assign out_csr_io_req_data[i] = in_csr_io_req_data;
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end
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assign in_csr_io_req_ready = out_csr_io_req_ready[request_id];
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reg [REQS_BITS-1:0] bus_rsp_sel;
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VX_fixed_arbiter #(
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.N(NUM_REQUESTS)
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) arbiter (
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.clk (clk),
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.reset (reset),
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.requests (in_csr_io_rsp_valid),
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.grant_index (bus_rsp_sel),
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`UNUSED_PIN (grant_valid),
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`UNUSED_PIN (grant_onehot)
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);
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assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel];
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assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel];
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign in_csr_io_rsp_ready[i] = out_csr_io_rsp_ready && (bus_rsp_sel == `REQS_BITS'(i));
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end
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end
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endmodule |