55 lines
2.0 KiB
Verilog
55 lines
2.0 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_arb (
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input wire clk,
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input wire reset,
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input wire csr_pipe_stall,
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VX_csr_req_if csr_core_req_if,
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VX_csr_io_req_if csr_io_req_if,
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VX_csr_req_if issued_csr_req_if,
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VX_wb_if csr_pipe_rsp_if,
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VX_wb_if csr_wb_if,
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VX_csr_io_rsp_if csr_io_rsp_if
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);
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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wire pick_core = (| csr_core_req_if.valid);
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// Which request to pick
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assign issued_csr_req_if.is_io = !pick_core;
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// Mux between core and io
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assign issued_csr_req_if.valid = pick_core ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}};
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assign issued_csr_req_if.is_csr = pick_core ? csr_core_req_if.is_csr : 1'b1;
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assign issued_csr_req_if.alu_op = pick_core ? csr_core_req_if.alu_op : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS);
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assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr;
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assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0);
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assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core);
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// Core arguments
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assign issued_csr_req_if.warp_num = csr_core_req_if.warp_num;
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assign issued_csr_req_if.rd = csr_core_req_if.rd;
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assign issued_csr_req_if.wb = csr_core_req_if.wb;
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// Core Writeback
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assign csr_wb_if.valid = csr_pipe_rsp_if.valid & {`NUM_THREADS{~csr_pipe_rsp_if.is_io}};
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assign csr_wb_if.data = csr_pipe_rsp_if.data;
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assign csr_wb_if.warp_num = csr_pipe_rsp_if.warp_num;
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assign csr_wb_if.rd = csr_pipe_rsp_if.rd;
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assign csr_wb_if.wb = csr_pipe_rsp_if.wb;
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assign csr_wb_if.curr_PC = csr_pipe_rsp_if.curr_PC;
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// CSR I/O response
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assign csr_io_rsp_if.valid = csr_pipe_rsp_if.valid[0] & csr_pipe_rsp_if.is_io;
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assign csr_io_rsp_if.data = csr_pipe_rsp_if.data[0];
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wire x = csr_io_rsp_if.ready;
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`UNUSED_VAR(x)
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endmodule
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