172 lines
5.2 KiB
Verilog
172 lines
5.2 KiB
Verilog
`include "VX_define.vh"
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module VX_back_end #(
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parameter CORE_ID = 0
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) (
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`SCOPE_SIGNALS_LSU_IO
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`SCOPE_SIGNALS_BE_IO
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input wire clk,
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input wire reset,
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VX_csr_io_req_if csr_io_req_if,
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VX_csr_io_rsp_if csr_io_rsp_if,
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input wire schedule_delay,
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VX_cache_core_req_if dcache_req_if,
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VX_cache_core_rsp_if dcache_rsp_if,
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VX_jal_rsp_if jal_rsp_if,
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VX_branch_rsp_if branch_rsp_if,
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VX_backend_req_if bckE_req_if,
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VX_wb_if writeback_if,
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VX_warp_ctl_if warp_ctl_if,
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output wire mem_delay,
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output wire exec_delay,
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output wire gpr_stage_delay,
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output wire ebreak
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);
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wire no_slot_mem;
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wire no_slot_exec;
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// LSU input + output
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VX_lsu_req_if lsu_req_if();
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VX_wb_if mem_wb_if();
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// Exec unit input + output
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VX_exec_unit_req_if exec_unit_req_if();
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VX_wb_if inst_exec_wb_if();
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// GPU unit input
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VX_gpu_inst_req_if gpu_inst_req_if();
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// CSR unit inputs
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VX_csr_req_if csr_req_if();
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VX_wb_if csr_wb_if();
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wire no_slot_csr;
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wire stall_gpr_csr;
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VX_gpr_stage gpr_stage (
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.clk (clk),
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.reset (reset),
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.schedule_delay (schedule_delay),
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.writeback_if (writeback_if),
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.bckE_req_if (bckE_req_if),
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// New
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.exec_unit_req_if (exec_unit_req_if),
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.lsu_req_if (lsu_req_if),
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.gpu_inst_req_if (gpu_inst_req_if),
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.csr_req_if (csr_req_if),
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.stall_gpr_csr (stall_gpr_csr),
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// End new
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.memory_delay (mem_delay),
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.exec_delay (exec_delay),
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.gpr_stage_delay (gpr_stage_delay)
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);
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assign ebreak = exec_unit_req_if.is_etype && (| exec_unit_req_if.valid);
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VX_lsu_unit #(
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.CORE_ID(CORE_ID)
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) lsu_unit (
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`SCOPE_SIGNALS_LSU_BIND
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.clk (clk),
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.reset (reset),
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.lsu_req_if (lsu_req_if),
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.mem_wb_if_p1 (mem_wb_if),
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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.delay (mem_delay),
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.no_slot_mem (no_slot_mem)
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);
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VX_exec_unit exec_unit (
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.clk (clk),
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.reset (reset),
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.exec_unit_req_if(exec_unit_req_if),
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.inst_exec_wb_if(inst_exec_wb_if),
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.jal_rsp_if (jal_rsp_if),
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.branch_rsp_if (branch_rsp_if),
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.delay (exec_delay),
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.no_slot_exec (no_slot_exec)
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);
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VX_gpu_inst gpu_inst (
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.gpu_inst_req_if(gpu_inst_req_if),
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.warp_ctl_if (warp_ctl_if)
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);
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VX_csr_req_if issued_csr_req_if();
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VX_wb_if csr_pipe_rsp_if();
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VX_csr_arb csr_arb (
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.clk (clk),
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.reset (reset),
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.csr_pipe_stall (stall_gpr_csr),
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.csr_core_req_if (csr_req_if),
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.csr_io_req_if (csr_io_req_if),
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.issued_csr_req_if(issued_csr_req_if),
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.csr_pipe_rsp_if (csr_pipe_rsp_if),
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.csr_wb_if (csr_wb_if),
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.csr_io_rsp_if (csr_io_rsp_if)
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);
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VX_csr_pipe #(
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.CORE_ID(CORE_ID)
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) csr_pipe (
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.clk (clk),
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.reset (reset),
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.no_slot_csr (no_slot_csr),
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.csr_req_if (issued_csr_req_if),
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.writeback_if (writeback_if),
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.csr_wb_if (csr_pipe_rsp_if),
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.stall_gpr_csr (stall_gpr_csr)
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);
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VX_writeback writeback (
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.clk (clk),
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.reset (reset),
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.mem_wb_if (mem_wb_if),
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.inst_exec_wb_if(inst_exec_wb_if),
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.csr_wb_if (csr_wb_if),
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.writeback_if (writeback_if),
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.no_slot_mem (no_slot_mem),
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.no_slot_exec (no_slot_exec),
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.no_slot_csr (no_slot_csr)
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);
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`SCOPE_ASSIGN(scope_decode_valid, bckE_req_if.valid);
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`SCOPE_ASSIGN(scope_decode_warp_num, bckE_req_if.warp_num);
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`SCOPE_ASSIGN(scope_decode_curr_PC, bckE_req_if.curr_PC);
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`SCOPE_ASSIGN(scope_decode_is_jal, bckE_req_if.is_jal);
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`SCOPE_ASSIGN(scope_decode_rs1, bckE_req_if.rs1);
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`SCOPE_ASSIGN(scope_decode_rs2, bckE_req_if.rs2);
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`SCOPE_ASSIGN(scope_execute_valid, exec_unit_req_if.valid);
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`SCOPE_ASSIGN(scope_execute_warp_num, exec_unit_req_if.warp_num);
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`SCOPE_ASSIGN(scope_execute_curr_PC, exec_unit_req_if.curr_PC);
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`SCOPE_ASSIGN(scope_execute_rd, exec_unit_req_if.rd);
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`SCOPE_ASSIGN(scope_execute_a, exec_unit_req_if.a_reg_data);
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`SCOPE_ASSIGN(scope_execute_b, exec_unit_req_if.b_reg_data);
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`SCOPE_ASSIGN(scope_writeback_valid, writeback_if.valid);
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`SCOPE_ASSIGN(scope_writeback_warp_num, writeback_if.warp_num);
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`SCOPE_ASSIGN(scope_writeback_curr_PC, writeback_if.curr_PC);
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`SCOPE_ASSIGN(scope_writeback_wb, writeback_if.wb);
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`SCOPE_ASSIGN(scope_writeback_rd, writeback_if.rd);
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`SCOPE_ASSIGN(scope_writeback_data, writeback_if.data);
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endmodule
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