84 lines
2.0 KiB
Verilog
84 lines
2.0 KiB
Verilog
`include "VX_define.vh"
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module VX_mult #(
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parameter WIDTHA = 1,
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parameter WIDTHB = 1,
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parameter WIDTHP = 1,
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parameter REP = "UNSIGNED",
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parameter PIPELINE = 0
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) (
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input clk,
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input reset,
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input clken,
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input [WIDTHA-1:0] dataa,
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input [WIDTHB-1:0] datab,
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output reg [WIDTHP-1:0] result
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);
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`ifdef QUARTUS
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lpm_mult #(
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.LPM_WIDTHA(WIDTHA),
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.LPM_WIDTHB(WIDTHB),
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.LPM_WIDTHP(WIDTHP),
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.LPM_REPRESENTATION(REP),
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.LPM_PIPELINE(PIPELINE),
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.DSP_BLOCK_BALANCING("LOGIC ELEMENTS"),
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.MAXIMIZE_SPEED(9)
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) quartus_mult (
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.clock(clk),
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.aclr(reset),
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.clken(clken),
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.dataa(dataa),
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.datab(datab),
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.result(result)
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);
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`else
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wire [WIDTHA-1:0] dataa_pipe_end;
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wire [WIDTHB-1:0] datab_pipe_end;
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if (PIPELINE == 0) begin
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assign dataa_pipe_end = dataa;
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assign datab_pipe_end = datab;
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end else begin
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reg [WIDTHA-1:0] dataa_pipe [0:PIPELINE-1];
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reg [WIDTHB-1:0] datab_pipe [0:PIPELINE-1];
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genvar i;
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for (i = 0; i < PIPELINE; i++) begin
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always @(posedge clk) begin
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if (reset) begin
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dataa_pipe[i] <= 0;
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datab_pipe[i] <= 0;
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end
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else if (clken) begin
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if (i == 0) begin
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dataa_pipe[0] <= dataa;
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datab_pipe[0] <= datab;
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end else begin
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dataa_pipe[i] <= dataa_pipe[i-1];
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datab_pipe[i] <= datab_pipe[i-1];
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end
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end
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end
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end
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assign dataa_pipe_end = dataa_pipe[PIPELINE-1];
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assign datab_pipe_end = datab_pipe[PIPELINE-1];
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end
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if (REP == "SIGNED") begin
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assign result = $signed(dataa_pipe_end) * $signed(datab_pipe_end);
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end
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else begin
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assign result = dataa_pipe_end * datab_pipe_end;
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end
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`endif
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endmodule: VX_mult
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