137 lines
2.6 KiB
C++
137 lines
2.6 KiB
C++
#pragma once
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#include <string>
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#include <vector>
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#include <list>
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#include <stack>
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#include <queue>
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#include <unordered_map>
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#include <memory>
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#include <set>
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#include <simobject.h>
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#include "debug.h"
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#include "types.h"
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#include "archdef.h"
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#include "decode.h"
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#include "mem.h"
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#include "warp.h"
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#include "pipeline.h"
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#include "cache.h"
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#include "ibuffer.h"
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#include "scoreboard.h"
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#include "exeunit.h"
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namespace vortex {
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class Core : public SimObject<Core> {
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public:
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Core(const SimContext& ctx, const ArchDef &arch, Word id);
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~Core();
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void attach_ram(RAM* ram);
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bool running() const;
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void step(uint64_t cycle);
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void printStats() const;
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Word id() const {
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return id_;
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}
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Warp& warp(int i) {
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return *warps_.at(i);
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}
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const Decoder& decoder() {
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return decoder_;
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}
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const ArchDef& arch() const {
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return arch_;
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}
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unsigned long stats_insts() const {
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return stats_insts_;
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}
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Word getIRegValue(int reg) const {
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return warps_.at(0)->getIRegValue(reg);
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}
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Word get_csr(Addr addr, int tid, int wid);
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void set_csr(Addr addr, Word value, int tid, int wid);
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void barrier(int bar_id, int count, int warp_id);
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Word icache_read(Addr, Size);
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Word dcache_read(Addr, Size);
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void dcache_write(Addr, Word, Size);
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void trigger_ebreak();
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bool check_ebreak() const;
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private:
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void fetch(uint64_t cycle);
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void decode(uint64_t cycle);
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void issue(uint64_t cycle);
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void execute(uint64_t cycle);
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void commit(uint64_t cycle);
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void warp_scheduler(uint64_t cycle);
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void writeToStdOut(Addr addr, Word data);
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Word id_;
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const ArchDef arch_;
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const Decoder decoder_;
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MemoryUnit mmu_;
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#ifdef SM_ENABLE
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RAM shared_mem_;
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#endif
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std::vector<std::shared_ptr<Warp>> warps_;
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std::vector<WarpMask> barriers_;
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std::vector<Word> csrs_;
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std::vector<Byte> fcsrs_;
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std::vector<IBuffer> ibuffers_;
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Scoreboard scoreboard_;
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std::vector<ExeUnit::Ptr> exe_units_;
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Cache::Ptr icache_;
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Cache::Ptr dcache_;
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Switch<MemReq, MemRsp>::Ptr l1_mem_switch_;
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PipelineStage fetch_stage_;
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PipelineStage decode_stage_;
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PipelineStage issue_stage_;
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PipelineStage execute_stage_;
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PipelineStage commit_stage_;
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HashTable<pipeline_state_t> pending_icache_;
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WarpMask stalled_warps_;
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uint32_t last_schedule_wid_;
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uint32_t issued_instrs_;
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uint32_t committed_instrs_;
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bool ebreak_;
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std::unordered_map<int, std::stringstream> print_bufs_;
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uint64_t stats_insts_;
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uint64_t stats_loads_;
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uint64_t stats_stores_;
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friend class LsuUnit;
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public:
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SlavePort<MemRsp> MemRspPort;
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MasterPort<MemReq> MemReqPort;
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};
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} // namespace vortex
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