131 lines
4.4 KiB
Verilog
131 lines
4.4 KiB
Verilog
`ifndef VX_CACHE_CONFIG
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`define VX_CACHE_CONFIG
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`include "../VX_define.v"
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// data tid rd wb warp_num read write
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`define vx_clog2(value) ((value == 1) ? 1 : $clog2(value))
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`define MRVQ_METADATA_SIZE (`WORD_SIZE + `vx_clog2(NUMBER_REQUESTS) + 5 + 2 + (`NW_M1 + 1) + 3 + 3)
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// 5 + 2 + 4 + 3 + 3 + 1
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`define REQ_INST_META_SIZE (5 + 2 + (`NW_M1+1) + 3 + 3 + `vx_clog2(NUMBER_REQUESTS))
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// `define vx_clog2_h(value, x) (value == (1 << x)) ? (x)
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// `define vx_clog2(value) (value == 0 ) ? 0 : \
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// (value == 1 ) ? 1 : \
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// `vx_clog2_h(value, 2 ) : \
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// `vx_clog2_h(value, 3 ) : \
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// `vx_clog2_h(value, 4 ) : \
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// `vx_clog2_h(value, 5 ) : \
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// `vx_clog2_h(value, 6 ) : \
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// `vx_clog2_h(value, 7 ) : \
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// `vx_clog2_h(value, 8 ) : \
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// `vx_clog2_h(value, 9 ) : \
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// `vx_clog2_h(value, 10) : \
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// `vx_clog2_h(value, 11) : \
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// `vx_clog2_h(value, 12) : \
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// `vx_clog2_h(value, 13) : \
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// `vx_clog2_h(value, 14) : \
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// `vx_clog2_h(value, 15) : \
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// `vx_clog2_h(value, 16) : \
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// `vx_clog2_h(value, 17) : \
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// `vx_clog2_h(value, 18) : \
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// `vx_clog2_h(value, 19) : \
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// `vx_clog2_h(value, 20) : \
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// `vx_clog2_h(value, 21) : \
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// `vx_clog2_h(value, 22) : \
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// `vx_clog2_h(value, 23) : \
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// `vx_clog2_h(value, 24) : \
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// `vx_clog2_h(value, 25) : \
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// `vx_clog2_h(value, 26) : \
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// `vx_clog2_h(value, 27) : \
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// `vx_clog2_h(value, 28) : \
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// `vx_clog2_h(value, 29) : \
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// `vx_clog2_h(value, 30) : \
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// `vx_clog2_h(value, 31) : \
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// 0
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`define WORD_SIZE (8*WORD_SIZE_BYTES)
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`define WORD_SIZE_RNG (`WORD_SIZE)-1:0
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// 128
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`define BANK_SIZE_BYTES CACHE_SIZE_BYTES/NUMBER_BANKS
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// 8
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`define BANK_LINE_COUNT (`BANK_SIZE_BYTES/BANK_LINE_SIZE_BYTES)
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// 4
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`define BANK_LINE_SIZE_WORDS (BANK_LINE_SIZE_BYTES / WORD_SIZE_BYTES)
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// 3:0
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`define BANK_LINE_SIZE_RNG `BANK_LINE_SIZE_WORDS-1:0
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// Offset is fixed
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`define OFFSET_ADDR_NUM_BITS 2
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`define OFFSET_SIZE_END 1
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`define OFFSET_ADDR_START 0
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`define OFFSET_ADDR_END 1
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`define OFFSET_ADDR_RNG `OFFSET_ADDR_END:`OFFSET_ADDR_START
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`define OFFSET_SIZE_RNG `OFFSET_SIZE_END:0
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// 2
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`define WORD_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_SIZE_WORDS))
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// 2
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`define WORD_SELECT_SIZE_END (`WORD_SELECT_NUM_BITS)
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// 2
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`define WORD_SELECT_ADDR_START (1+`OFFSET_ADDR_END)
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// 3
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`define WORD_SELECT_ADDR_END (`WORD_SELECT_SIZE_END+`OFFSET_ADDR_END)
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// 3:2
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`define WORD_SELECT_ADDR_RNG `WORD_SELECT_ADDR_END:`WORD_SELECT_ADDR_START
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`define WORD_SELECT_SIZE_RNG `WORD_SELECT_SIZE_END-1:0
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// 3
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`define BANK_SELECT_NUM_BITS (`vx_clog2(NUMBER_BANKS))
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// 3
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`define BANK_SELECT_SIZE_END (`BANK_SELECT_NUM_BITS)
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// 4
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`define BANK_SELECT_ADDR_START (1+`WORD_SELECT_ADDR_END)
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// 6
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`define BANK_SELECT_ADDR_END (`BANK_SELECT_SIZE_END+`BANK_SELECT_ADDR_START-1)
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// 6:4
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`define BANK_SELECT_ADDR_RNG `BANK_SELECT_ADDR_END:`BANK_SELECT_ADDR_START
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// 2:0
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`define BANK_SELECT_SIZE_RNG `BANK_SELECT_SIZE_END-1:0
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// 3
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`define LINE_SELECT_NUM_BITS (`vx_clog2(`BANK_LINE_COUNT))
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// 3
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`define LINE_SELECT_SIZE_END (`LINE_SELECT_NUM_BITS)
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// 7
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`define LINE_SELECT_ADDR_START (1+`BANK_SELECT_ADDR_END)
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// 9
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`define LINE_SELECT_ADDR_END (`LINE_SELECT_SIZE_END+`LINE_SELECT_ADDR_START-1)
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// 9:7
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`define LINE_SELECT_ADDR_RNG `LINE_SELECT_ADDR_END:`LINE_SELECT_ADDR_START
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// 2:0
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`define LINE_SELECT_SIZE_RNG `LINE_SELECT_SIZE_END-1:0
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// 10
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`define TAG_SELECT_ADDR_START (1+`LINE_SELECT_ADDR_END)
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// 31:10
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`define TAG_SELECT_ADDR_RNG 31:`TAG_SELECT_ADDR_START
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// 22
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`define TAG_SELECT_NUM_BITS (32-`TAG_SELECT_ADDR_START)
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// 22
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`define TAG_SELECT_SIZE_END (`TAG_SELECT_NUM_BITS)
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// 21:0
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`define TAG_SELECT_SIZE_RNG `TAG_SELECT_SIZE_END-1:0
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`define BASE_ADDR_MASK (~((1<<(`WORD_SELECT_ADDR_END+1))-1))
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`endif
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