13 lines
180 B
Verilog
13 lines
180 B
Verilog
`ifndef VX_WSTALL_IF
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`define VX_WSTALL_IF
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`include "VX_define.vh"
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interface VX_wstall_if();
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wire valid;
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wire [`NW_BITS-1:0] wid;
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endinterface
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`endif |