266 lines
9.8 KiB
Systemverilog
266 lines
9.8 KiB
Systemverilog
`include "VX_tex_define.vh"
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module VX_tex_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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// PERF
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`ifdef PERF_ENABLE
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VX_perf_tex_if.master perf_tex_if,
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`endif
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// Texture unit <-> Memory Unit
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VX_dcache_req_if.master dcache_req_if,
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VX_dcache_rsp_if.slave dcache_rsp_if,
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// Inputs
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VX_tex_req_if.slave tex_req_if,
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VX_tex_csr_if.slave tex_csr_if,
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// Outputs
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VX_tex_rsp_if.master tex_rsp_if
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);
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localparam REQ_INFO_W = `NR_BITS + 1 + `NW_BITS + 32 + `UUID_BITS;
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localparam BLEND_FRAC_W = (2 * `NUM_THREADS * `TEX_BLEND_FRAC);
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reg [$clog2(`NUM_TEX_UNITS)-1:0] csr_tex_unit;
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reg [`TEX_MIPOFF_BITS-1:0] tex_mipoff [`NUM_TEX_UNITS-1:0][(`TEX_LOD_MAX+1)-1:0];
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reg [1:0][`TEX_LOD_BITS-1:0] tex_logdims [`NUM_TEX_UNITS-1:0];
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reg [1:0][`TEX_WRAP_BITS-1:0] tex_wraps [`NUM_TEX_UNITS-1:0];
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reg [`TEX_ADDR_BITS-1:0] tex_baddr [`NUM_TEX_UNITS-1:0];
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reg [`TEX_FORMAT_BITS-1:0] tex_format [`NUM_TEX_UNITS-1:0];
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reg [`TEX_FILTER_BITS-1:0] tex_filter [`NUM_TEX_UNITS-1:0];
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// CSRs programming
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always @(posedge clk) begin
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if (tex_csr_if.write_enable) begin
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case (tex_csr_if.write_addr)
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`CSR_TEX_UNIT: begin
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csr_tex_unit <= tex_csr_if.write_data[$clog2(`NUM_TEX_UNITS)-1:0];
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end
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`CSR_TEX_ADDR: begin
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tex_baddr[csr_tex_unit] <= tex_csr_if.write_data[`TEX_ADDR_BITS-1:0];
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end
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`CSR_TEX_FORMAT: begin
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tex_format[csr_tex_unit] <= tex_csr_if.write_data[`TEX_FORMAT_BITS-1:0];
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end
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`CSR_TEX_WRAPU: begin
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tex_wraps[csr_tex_unit][0] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0];
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end
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`CSR_TEX_WRAPV: begin
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tex_wraps[csr_tex_unit][1] <= tex_csr_if.write_data[`TEX_WRAP_BITS-1:0];
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end
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`CSR_TEX_FILTER: begin
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tex_filter[csr_tex_unit] <= tex_csr_if.write_data[`TEX_FILTER_BITS-1:0];
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end
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`CSR_TEX_WIDTH: begin
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tex_logdims[csr_tex_unit][0] <= tex_csr_if.write_data[`TEX_LOD_BITS-1:0];
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end
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`CSR_TEX_HEIGHT: begin
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tex_logdims[csr_tex_unit][1] <= tex_csr_if.write_data[`TEX_LOD_BITS-1:0];
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end
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default: begin
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for (integer j = 0; j <= `TEX_LOD_MAX; ++j) begin
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`IGNORE_WARNINGS_BEGIN
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if (tex_csr_if.write_addr == `CSR_TEX_MIPOFF(j)) begin
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`IGNORE_WARNINGS_END
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tex_mipoff[csr_tex_unit][j] <= tex_csr_if.write_data[`TEX_MIPOFF_BITS-1:0];
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end
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end
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end
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endcase
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end
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end
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wire [`UUID_BITS-1:0] write_uuid = tex_csr_if.write_uuid;
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`UNUSED_VAR (write_uuid);
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// mipmap attributes
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wire [`NUM_THREADS-1:0][`TEX_LOD_BITS-1:0] mip_level;
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wire [`NUM_THREADS-1:0][`TEX_MIPOFF_BITS-1:0] sel_mipoff;
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wire [`NUM_THREADS-1:0][1:0][`TEX_LOD_BITS-1:0] sel_logdims;
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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wire [`NTEX_BITS-1:0] unit = tex_req_if.unit[`NTEX_BITS-1:0];
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assign mip_level[i] = tex_req_if.lod[i][`TEX_LOD_BITS-1:0];
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assign sel_mipoff[i] = tex_mipoff[unit][mip_level[i]];
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assign sel_logdims[i][0] = tex_logdims[unit][0];
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assign sel_logdims[i][1] = tex_logdims[unit][1];
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end
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// address generation
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wire mem_req_valid;
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wire [`NUM_THREADS-1:0] mem_req_tmask;
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wire [`TEX_FILTER_BITS-1:0] mem_req_filter;
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wire [`TEX_LGSTRIDE_BITS-1:0] mem_req_lgstride;
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wire [`NUM_THREADS-1:0][1:0][`TEX_BLEND_FRAC-1:0] mem_req_blends;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_req_addr;
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wire [`NUM_THREADS-1:0][31:0] mem_req_baseaddr;
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wire [(`TEX_FORMAT_BITS + REQ_INFO_W)-1:0] mem_req_info;
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wire mem_req_ready;
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VX_tex_addr #(
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.CORE_ID (CORE_ID),
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.REQ_INFOW (`TEX_FORMAT_BITS + REQ_INFO_W),
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.NUM_REQS (`NUM_THREADS)
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) tex_addr (
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.clk (clk),
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.reset (reset),
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.req_valid (tex_req_if.valid),
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.req_tmask (tex_req_if.tmask),
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.req_coords (tex_req_if.coords),
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.req_format (tex_format[tex_req_if.unit]),
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.req_filter (tex_filter[tex_req_if.unit]),
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.req_wraps (tex_wraps[tex_req_if.unit]),
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.req_baseaddr(tex_baddr[tex_req_if.unit]),
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.mip_level (mip_level),
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.req_mipoff (sel_mipoff),
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.req_logdims(sel_logdims),
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.req_info ({tex_format[tex_req_if.unit], tex_req_if.rd, tex_req_if.wb, tex_req_if.wid, tex_req_if.PC, tex_req_if.uuid}),
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.req_ready (tex_req_if.ready),
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.rsp_valid (mem_req_valid),
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.rsp_tmask (mem_req_tmask),
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.rsp_filter (mem_req_filter),
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.rsp_lgstride(mem_req_lgstride),
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.rsp_baseaddr(mem_req_baseaddr),
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.rsp_addr (mem_req_addr),
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.rsp_blends (mem_req_blends),
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.rsp_info (mem_req_info),
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.rsp_ready (mem_req_ready)
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);
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// retrieve texel values from memory
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wire mem_rsp_valid;
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wire [`NUM_THREADS-1:0] mem_rsp_tmask;
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wire [`NUM_THREADS-1:0][3:0][31:0] mem_rsp_data;
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wire [(BLEND_FRAC_W + `TEX_FORMAT_BITS + REQ_INFO_W)-1:0] mem_rsp_info;
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wire mem_rsp_ready;
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VX_tex_mem #(
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.CORE_ID (CORE_ID),
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.REQ_INFOW (BLEND_FRAC_W + `TEX_FORMAT_BITS + REQ_INFO_W),
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.NUM_REQS (`NUM_THREADS)
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) tex_mem (
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.clk (clk),
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.reset (reset),
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// memory interface
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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// inputs
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.req_valid (mem_req_valid),
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.req_tmask (mem_req_tmask),
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.req_filter(mem_req_filter),
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.req_lgstride(mem_req_lgstride),
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.req_baseaddr(mem_req_baseaddr),
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.req_addr (mem_req_addr),
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.req_info ({mem_req_blends, mem_req_info}),
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.req_ready (mem_req_ready),
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// outputs
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.rsp_valid (mem_rsp_valid),
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.rsp_tmask (mem_rsp_tmask),
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.rsp_data (mem_rsp_data),
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.rsp_info (mem_rsp_info),
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.rsp_ready (mem_rsp_ready)
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);
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// apply sampler
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VX_tex_sampler #(
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.CORE_ID (CORE_ID),
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.REQ_INFOW (REQ_INFO_W),
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.NUM_REQS (`NUM_THREADS)
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) tex_sampler (
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.clk (clk),
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.reset (reset),
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// inputs
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.req_valid (mem_rsp_valid),
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.req_tmask (mem_rsp_tmask),
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.req_data (mem_rsp_data),
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.req_blends (mem_rsp_info[(REQ_INFO_W+`TEX_FORMAT_BITS) +: BLEND_FRAC_W]),
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.req_format (mem_rsp_info[REQ_INFO_W +: `TEX_FORMAT_BITS]),
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.req_info (mem_rsp_info[0 +: REQ_INFO_W]),
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.req_ready (mem_rsp_ready),
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// outputs
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.rsp_valid (tex_rsp_if.valid),
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.rsp_tmask (tex_rsp_if.tmask),
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.rsp_data (tex_rsp_if.data),
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.rsp_info ({tex_rsp_if.rd, tex_rsp_if.wb, tex_rsp_if.wid, tex_rsp_if.PC, tex_rsp_if.uuid}),
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.rsp_ready (tex_rsp_if.ready)
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);
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`ifdef PERF_ENABLE
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wire [$clog2(`NUM_THREADS+1)-1:0] perf_mem_req_per_cycle;
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wire [$clog2(`NUM_THREADS+1)-1:0] perf_mem_rsp_per_cycle;
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wire [`NUM_THREADS-1:0] perf_mem_req_per_mask = dcache_req_if.valid & dcache_req_if.ready;
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wire [`NUM_THREADS-1:0] perf_mem_rsp_per_mask = dcache_rsp_if.tmask & {`NUM_THREADS{dcache_rsp_if.valid & dcache_rsp_if.ready}};
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`POP_COUNT(perf_mem_req_per_cycle, perf_mem_req_per_mask);
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`POP_COUNT(perf_mem_rsp_per_cycle, perf_mem_rsp_per_mask);
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reg [`PERF_CTR_BITS-1:0] perf_pending_reads;
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wire [$clog2(`NUM_THREADS+1)+1-1:0] perf_pending_reads_cycle = perf_mem_req_per_cycle - perf_mem_rsp_per_cycle;
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always @(posedge clk) begin
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if (reset) begin
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perf_pending_reads <= 0;
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end else begin
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perf_pending_reads <= perf_pending_reads + `PERF_CTR_BITS'($signed(perf_pending_reads_cycle));
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end
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end
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reg [`PERF_CTR_BITS-1:0] perf_mem_reads;
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reg [`PERF_CTR_BITS-1:0] perf_mem_latency;
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always @(posedge clk) begin
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if (reset) begin
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perf_mem_reads <= 0;
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perf_mem_latency <= 0;
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end else begin
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perf_mem_reads <= perf_mem_reads + `PERF_CTR_BITS'(perf_mem_req_per_cycle);
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perf_mem_latency <= perf_mem_latency + `PERF_CTR_BITS'(perf_pending_reads);
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end
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end
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assign perf_tex_if.mem_reads = perf_mem_reads;
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assign perf_tex_if.mem_latency = perf_mem_latency;
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`endif
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`ifdef DBG_TRACE_TEX
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always @(posedge clk) begin
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if (tex_csr_if.write_enable) begin
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dpi_trace("%d: core%0d-tex-csr: unit=%0d, state=", $time, CORE_ID, csr_tex_unit);
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trace_tex_state(tex_csr_if.write_addr);
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dpi_trace(", data=%0h (#%0d)\n", tex_csr_if.write_data, tex_csr_if.write_uuid);
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end
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if (tex_req_if.valid && tex_req_if.ready) begin
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dpi_trace("%d: core%0d-tex-req: wid=%0d, PC=%0h, tmask=%b, unit=%0d, lod=%0h, u=",
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$time, CORE_ID, tex_req_if.wid, tex_req_if.PC, tex_req_if.tmask, tex_req_if.unit, tex_req_if.lod);
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`TRACE_ARRAY1D(tex_req_if.coords[0], `NUM_THREADS);
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dpi_trace(", v=");
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`TRACE_ARRAY1D(tex_req_if.coords[1], `NUM_THREADS);
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dpi_trace(" (#%0d)\n", tex_req_if.uuid);
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end
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if (tex_rsp_if.valid && tex_rsp_if.ready) begin
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dpi_trace("%d: core%0d-tex-rsp: wid=%0d, PC=%0h, tmask=%b, data=",
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$time, CORE_ID, tex_rsp_if.wid, tex_rsp_if.PC, tex_rsp_if.tmask);
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`TRACE_ARRAY1D(tex_rsp_if.data, `NUM_THREADS);
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dpi_trace(" (#%0d)\n", tex_rsp_if.uuid);
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end
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end
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`endif
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endmodule |