107 lines
3.3 KiB
Verilog
107 lines
3.3 KiB
Verilog
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`include "VX_define.v"
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module VX_lsu (
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input wire clk,
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input wire reset,
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input wire no_slot_mem,
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VX_lsu_req_inter VX_lsu_req,
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// Write back to GPR
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VX_inst_mem_wb_inter VX_mem_wb,
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VX_dcache_response_inter VX_dcache_rsp,
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VX_dcache_request_inter VX_dcache_req,
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output wire out_delay
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);
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// VX_inst_mem_wb_inter VX_mem_wb_temp();
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assign out_delay = VX_dcache_rsp.delay || no_slot_mem;
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// Generate Addresses
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wire[`NT_M1:0][31:0] address;
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VX_lsu_addr_gen VX_lsu_addr_gen
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(
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.base_address(VX_lsu_req.base_address),
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.offset (VX_lsu_req.offset),
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.address (address)
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);
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wire[`NT_M1:0][31:0] use_address;
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wire[`NT_M1:0][31:0] use_store_data;
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wire[`NT_M1:0] use_valid;
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wire[2:0] use_mem_read;
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wire[2:0] use_mem_write;
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wire[4:0] use_rd;
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wire[`NW_M1:0] use_warp_num;
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wire[1:0] use_wb;
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wire[31:0] use_pc;
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wire zero = 0;
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VX_generic_register #(.N(45 + `NW_M1 + 1 + `NT*65)) lsu_buffer(
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.clk (clk),
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.reset(reset),
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.stall(out_delay),
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.flush(zero),
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.in ({address , VX_lsu_req.store_data, VX_lsu_req.valid, VX_lsu_req.mem_read, VX_lsu_req.mem_write, VX_lsu_req.rd, VX_lsu_req.warp_num, VX_lsu_req.wb, VX_lsu_req.lsu_pc}),
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.out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc })
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);
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genvar index;
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for (index = 0; index <= `NT_M1; index = index + 1) begin
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assign VX_dcache_req.out_cache_driver_in_address[index] = use_address[index];
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assign VX_dcache_req.out_cache_driver_in_data[index] = use_store_data[index];
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assign VX_dcache_req.out_cache_driver_in_valid[index] = (use_valid[index]);
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assign VX_mem_wb.loaded_data[index] = VX_dcache_rsp.in_cache_driver_out_data[index];
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end
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assign VX_dcache_req.out_cache_driver_in_mem_read = use_mem_read;
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assign VX_dcache_req.out_cache_driver_in_mem_write = use_mem_write;
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assign VX_mem_wb.rd = use_rd;
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assign VX_mem_wb.wb = use_wb & {!VX_dcache_rsp.delay, !VX_dcache_rsp.delay};
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assign VX_mem_wb.wb_valid = use_valid;
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assign VX_mem_wb.wb_warp_num = use_warp_num;
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assign VX_mem_wb.mem_wb_pc = use_pc;
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// integer curr_t;
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// always @(negedge clk) begin
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// for (int curr_t = 0; curr_t < `NT; curr_t=curr_t+1)
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// if ((VX_dcache_req.out_cache_driver_in_valid[curr_t]) && !out_delay) begin
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// if (VX_dcache_req.out_cache_driver_in_mem_read != `NO_MEM_READ) begin
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// $display("Reading addr: %x val: %x", address[0], VX_mem_wb.loaded_data[0]);
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// end
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// if (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE) begin
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// $display("Writing addr: %x val: %x", address[0], VX_dcache_req.out_cache_driver_in_data[0]);
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// end
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// end
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// end
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// wire zero_temp = 0;
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// VX_generic_register #(.N(142)) register_wb_data
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// (
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// .clk (clk),
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// .reset(reset),
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// .stall(zero_temp),
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// .flush(out_delay),
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// .in ({VX_mem_wb_temp.loaded_data, VX_mem_wb_temp.rd, VX_mem_wb_temp.wb, VX_mem_wb_temp.wb_valid, VX_mem_wb_temp.wb_warp_num}),
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// .out ({VX_mem_wb.loaded_data , VX_mem_wb.rd , VX_mem_wb.wb , VX_mem_wb.wb_valid , VX_mem_wb.wb_warp_num })
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// );
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endmodule // Memory
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