86 lines
2.3 KiB
Verilog
86 lines
2.3 KiB
Verilog
`include "VX_platform.vh"
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module VX_index_buffer #(
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parameter DATAW = 1,
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parameter SIZE = 1,
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parameter FASTRAM = 1,
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parameter ADDRW = `LOG2UP(SIZE)
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) (
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input wire clk,
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input wire reset,
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output wire [ADDRW-1:0] write_addr,
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input wire [DATAW-1:0] write_data,
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input wire acquire_slot,
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input wire [ADDRW-1:0] read_addr,
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output wire [DATAW-1:0] read_data,
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input wire [ADDRW-1:0] release_addr,
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input wire release_slot,
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output wire full
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);
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reg [SIZE-1:0] free_slots, free_slots_n;
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reg [ADDRW-1:0] write_addr_r;
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reg full_r;
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wire free_valid;
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wire [ADDRW-1:0] free_index;
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VX_priority_encoder #(
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.N (SIZE)
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) free_slots_encoder (
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.data_in (free_slots_n),
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.index (free_index),
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`UNUSED_PIN (onehot),
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.valid_out (free_valid)
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);
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always @(*) begin
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free_slots_n = free_slots;
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if (release_slot) begin
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free_slots_n[release_addr] = 1;
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end
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if (acquire_slot) begin
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assert(1 == free_slots[write_addr]) else $error("%t: acquiring used slot at port %d", $time, write_addr);
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free_slots_n[write_addr_r] = 0;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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write_addr_r <= ADDRW'(1'b0);
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free_slots <= {SIZE{1'b1}};
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full_r <= 1'b0;
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end else begin
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if (release_slot) begin
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assert(0 == free_slots[release_addr]) else $error("%t: releasing invalid slot at port %d", $time, release_addr);
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end
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if (acquire_slot || full_r) begin
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write_addr_r <= free_index;
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end
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free_slots <= free_slots_n;
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full_r <= ~free_valid;
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end
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end
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VX_dp_ram #(
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.DATAW(DATAW),
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.SIZE(SIZE),
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.RWCHECK(1),
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.FASTRAM(FASTRAM)
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) data_table (
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.clk(clk),
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.waddr(write_addr),
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.raddr(read_addr),
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.wren(acquire_slot),
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.byteen(1'b1),
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.rden(1'b1),
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.din(write_data),
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.dout(read_data)
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);
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assign write_addr = write_addr_r;
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assign full = full_r;
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endmodule |