55 lines
1.5 KiB
Verilog
55 lines
1.5 KiB
Verilog
`include "VX_platform.vh"
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module VX_rr_arbiter #(
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parameter N = 1
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) (
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input wire clk,
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input wire reset,
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input wire [N-1:0] requests,
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output wire [`LOG2UP(N)-1:0] grant_index,
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output wire [N-1:0] grant_onehot,
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output wire grant_valid
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);
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if (N == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign grant_index = 0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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reg [`CLOG2(N)-1:0] grant_table [0:N-1];
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reg [`CLOG2(N)-1:0] state;
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reg [N-1:0] grant_onehot_r;
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always @(*) begin
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for (integer i = 0; i < N; i++) begin
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grant_table[i] = `CLOG2(N)'(i);
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for (integer j = 0; j < N; j++) begin
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if (requests[(i+j) % N]) begin
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grant_table[i] = `CLOG2(N)'((i+j) % N);
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end
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end
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end
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grant_onehot_r = N'(0);
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grant_onehot_r[grant_index] = 1;
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end
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always @(posedge clk) begin
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if (reset) begin
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state <= 0;
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end else begin
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state <= grant_index;
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end
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end
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assign grant_index = grant_table[state];
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assign grant_onehot = grant_onehot_r;
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assign grant_valid = (| requests);
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end
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endmodule |