68 lines
1.9 KiB
Verilog
68 lines
1.9 KiB
Verilog
`include "VX_platform.vh"
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module VX_matrix_arbiter #(
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parameter N = 1
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) (
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input wire clk,
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input wire reset,
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input wire [N-1:0] requests,
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output wire [`LOG2UP(N)-1:0] grant_index,
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output wire [N-1:0] grant_onehot,
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output wire grant_valid
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);
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if (N == 1) begin
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`UNUSED_VAR (clk)
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`UNUSED_VAR (reset)
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assign grant_index = 0;
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assign grant_onehot = requests;
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assign grant_valid = requests[0];
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end else begin
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reg [N-1:1] state [0:N-1];
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wire [N-1:0] pri [0:N-1];
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for (genvar i = 0; i < N; i++) begin
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for (genvar j = 0; j < N; j++) begin
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if (j > i) begin
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assign pri[j][i] = requests[i] && state[i][j];
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end
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else if (j < i) begin
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assign pri[j][i] = requests[i] && !state[j][i];
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end
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else begin
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assign pri[j][i] = 0;
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end
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end
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assign grant_onehot[i] = requests[i] && !(| pri[i]);
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end
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for (genvar i = 0; i < N; i++) begin
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for (genvar j = i + 1; j < N; j++) begin
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always @(posedge clk) begin
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if (reset) begin
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state[i][j] <= 0;
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end else begin
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state[i][j] <= (state[i][j] || grant_onehot[j]) && !grant_onehot[i];
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end
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end
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end
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end
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VX_onehot_encoder #(
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.N(N)
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) encoder (
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.onehot (grant_onehot),
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`UNUSED_PIN (valid),
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.value (grant_index)
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);
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assign grant_valid = (| requests);
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end
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endmodule |