66 lines
1.7 KiB
Verilog
66 lines
1.7 KiB
Verilog
`include "VX_platform.vh"
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module VX_elastic_buffer #(
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parameter DATAW = 1,
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parameter SIZE = 2,
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parameter BUFFERED = 1
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) (
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input wire clk,
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input wire reset,
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input wire valid_in,
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output wire ready_in,
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input wire [DATAW-1:0] data_in,
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output wire [DATAW-1:0] data_out,
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input wire ready_out,
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output wire valid_out
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);
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if (0 == SIZE) begin
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reg [DATAW-1:0] skid_buffer;
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reg skid_valid;
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always @(posedge clk) begin
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if (reset) begin
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skid_valid <= 0;
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end else begin
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if (valid_in && ~ready_out) begin
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assert(~skid_valid);
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skid_buffer <= data_in;
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skid_valid <= 1;
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end
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if (ready_out) begin
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skid_valid <= 0;
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end
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end
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end
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assign ready_in = ready_out || ~skid_valid;
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assign data_out = skid_valid ? skid_buffer : data_in;
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assign valid_out = valid_in || skid_valid;
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end else begin
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wire empty, full;
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VX_generic_queue #(
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.DATAW (DATAW),
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.SIZE (SIZE),
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.BUFFERED (BUFFERED)
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) queue (
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.clk (clk),
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.reset (reset),
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.push (valid_in),
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.pop (ready_out),
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.data_in(data_in),
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.data_out(data_out),
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.empty (empty),
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.full (full),
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`UNUSED_PIN (size)
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);
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assign ready_in = ~full;
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assign valid_out = ~empty;
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end
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endmodule |