102 lines
4.5 KiB
Verilog
102 lines
4.5 KiB
Verilog
`include "VX_define.vh"
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module VX_issue_demux (
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// inputs
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VX_issue_if issue_if,
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// outputs
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VX_alu_req_if alu_req_if,
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VX_bru_req_if bru_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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// ALU unit
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assign alu_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_ALU);
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assign alu_req_if.issue_tag = issue_if.issue_tag;
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assign alu_req_if.wid = issue_if.wid;
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assign alu_req_if.thread_mask = issue_if.thread_mask;
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assign alu_req_if.curr_PC = issue_if.curr_PC;
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assign alu_req_if.op = `ALU_OP(issue_if.ex_op);
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assign alu_req_if.rs1_is_PC = issue_if.rs1_is_PC;
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assign alu_req_if.rs2_is_imm = issue_if.rs2_is_imm;
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assign alu_req_if.imm = issue_if.imm;
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assign alu_req_if.rs1_data = issue_if.rs1_data;
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assign alu_req_if.rs2_data = issue_if.rs2_data;
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// BRU unit
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assign bru_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_BRU);
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assign bru_req_if.issue_tag = issue_if.issue_tag;
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assign bru_req_if.wid = issue_if.wid;
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assign bru_req_if.thread_mask = issue_if.thread_mask;
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assign bru_req_if.curr_PC = issue_if.curr_PC;
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assign bru_req_if.op = `BRU_OP(issue_if.ex_op);
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assign bru_req_if.rs1_is_PC = issue_if.rs1_is_PC;
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assign bru_req_if.rs1_data = issue_if.rs1_data[issue_if.tid];
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assign bru_req_if.rs2_data = issue_if.rs2_data[issue_if.tid];
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assign bru_req_if.offset = issue_if.imm;
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// LSU unit
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assign lsu_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_LSU);
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assign lsu_req_if.issue_tag = issue_if.issue_tag;
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assign lsu_req_if.wid = issue_if.wid;
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assign lsu_req_if.thread_mask = issue_if.thread_mask;
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assign lsu_req_if.curr_PC = issue_if.curr_PC;
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assign lsu_req_if.rw = `LSU_RW(issue_if.ex_op);
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assign lsu_req_if.byteen = `LSU_BE(issue_if.ex_op);
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assign lsu_req_if.base_addr = issue_if.rs1_data;
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assign lsu_req_if.store_data = issue_if.rs2_data;
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assign lsu_req_if.offset = issue_if.imm;
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assign lsu_req_if.rd = issue_if.rd;
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assign lsu_req_if.wb = issue_if.wb;
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// CSR unit
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assign csr_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_CSR);
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assign csr_req_if.issue_tag = issue_if.issue_tag;
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assign csr_req_if.wid = issue_if.wid;
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assign csr_req_if.thread_mask = issue_if.thread_mask;
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assign csr_req_if.curr_PC = issue_if.curr_PC;
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assign csr_req_if.op = `CSR_OP(issue_if.ex_op);
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assign csr_req_if.csr_addr = issue_if.imm[`CSR_ADDR_BITS-1:0];
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assign csr_req_if.csr_mask = issue_if.rs2_is_imm ? 32'(issue_if.rs1) : issue_if.rs1_data[0];
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assign csr_req_if.is_io = 1'b0;
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// MUL unit
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`ifdef EXT_M_ENABLE
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assign mul_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_MUL);
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assign mul_req_if.issue_tag = issue_if.issue_tag;
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assign mul_req_if.wid = issue_if.wid;
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assign mul_req_if.thread_mask = issue_if.thread_mask;
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assign mul_req_if.curr_PC = issue_if.curr_PC;
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assign mul_req_if.op = `MUL_OP(issue_if.ex_op);
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assign mul_req_if.rs1_data = issue_if.rs1_data;
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assign mul_req_if.rs2_data = issue_if.rs2_data;
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`endif
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// FPU unit
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`ifdef EXT_F_ENABLE
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assign fpu_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_FPU);
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assign fpu_req_if.issue_tag = issue_if.issue_tag;
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assign fpu_req_if.wid = issue_if.wid;
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assign fpu_req_if.thread_mask = issue_if.thread_mask;
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assign fpu_req_if.curr_PC = issue_if.curr_PC;
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assign fpu_req_if.op = `FPU_OP(issue_if.ex_op);
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assign fpu_req_if.frm = issue_if.frm;
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assign fpu_req_if.rs1_data = issue_if.rs1_data;
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assign fpu_req_if.rs2_data = issue_if.rs2_data;
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assign fpu_req_if.rs3_data = issue_if.rs3_data;
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`endif
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// GPU unit
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assign gpu_req_if.valid = issue_if.valid && (issue_if.ex_type == `EX_GPU);
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assign gpu_req_if.issue_tag = issue_if.issue_tag;
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assign gpu_req_if.wid = issue_if.wid;
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assign gpu_req_if.thread_mask = issue_if.thread_mask;
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assign gpu_req_if.curr_PC = issue_if.curr_PC;
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assign gpu_req_if.op = `GPU_OP(issue_if.ex_op);
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assign gpu_req_if.rs1_data = issue_if.rs1_data;
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assign gpu_req_if.rs2_data = issue_if.rs2_data[0];
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endmodule |