136 lines
6.3 KiB
Verilog
136 lines
6.3 KiB
Verilog
`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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VX_cmt_to_issue_if cmt_to_issue_if,
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VX_alu_req_if alu_req_if,
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VX_bru_req_if bru_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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wire [`ISTAG_BITS-1:0] issue_tag;
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wire schedule_delay;
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VX_gpr_read_if gpr_read_if();
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assign gpr_read_if.valid = decode_if.valid && ~schedule_delay;
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assign gpr_read_if.wid = decode_if.wid;
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assign gpr_read_if.rs1 = decode_if.rs1;
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assign gpr_read_if.rs2 = decode_if.rs2;
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assign gpr_read_if.rs3 = decode_if.rs3;
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assign gpr_read_if.use_rs3 = decode_if.use_rs3;
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wire ex_busy = (~alu_req_if.ready && (decode_if.ex_type == `EX_ALU))
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|| (~bru_req_if.ready && (decode_if.ex_type == `EX_BRU))
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|| (~lsu_req_if.ready && (decode_if.ex_type == `EX_LSU))
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|| (~csr_req_if.ready && (decode_if.ex_type == `EX_CSR))
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`ifdef EXT_M_ENABLE
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|| (~mul_req_if.ready && (decode_if.ex_type == `EX_MUL))
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`endif
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`ifdef EXT_F_ENABLE
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|| (~fpu_req_if.ready && (decode_if.ex_type == `EX_FPU))
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`endif
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|| (~gpu_req_if.ready && (decode_if.ex_type == `EX_GPU));
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VX_scoreboard #(
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.CORE_ID(CORE_ID)
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) scoreboard (
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.clk (clk),
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.reset (reset),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.cmt_to_issue_if(cmt_to_issue_if),
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.ex_busy (ex_busy),
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.issue_tag (issue_tag),
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.schedule_delay (schedule_delay)
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);
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (reset),
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.writeback_if (writeback_if),
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.gpr_read_if (gpr_read_if)
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);
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VX_issue_if issue_if();
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assign issue_if.rs1_data = gpr_read_if.rs1_data;
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assign issue_if.rs2_data = gpr_read_if.rs2_data;
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assign issue_if.rs3_data = gpr_read_if.rs3_data;
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wire [`NT_BITS-1:0] tid;
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VX_priority_encoder #(
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.N(`NUM_THREADS)
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) sel_src (
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.data_in (decode_if.thread_mask),
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.data_out (tid),
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`UNUSED_PIN (valid_out)
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);
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wire stall = schedule_delay || ~gpr_read_if.ready;
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wire flush = stall; // clear output on stall
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + `NUM_THREADS + 32 + `NR_BITS + `NR_BITS + 32 + 1 + 1 + `EX_BITS + `OP_BITS + 1 + `FRM_BITS + `NT_BITS)
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) issue_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (flush),
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.in ({decode_if.valid, issue_tag, decode_if.wid, decode_if.thread_mask, decode_if.curr_PC, decode_if.rd, decode_if.rs1, decode_if.imm, decode_if.rs1_is_PC, decode_if.rs2_is_imm, decode_if.ex_type, decode_if.ex_op, decode_if.wb, decode_if.frm, tid}),
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.out ({issue_if.valid, issue_if.issue_tag, issue_if.wid, issue_if.thread_mask, issue_if.curr_PC, issue_if.rd, issue_if.rs1, issue_if.imm, issue_if.rs1_is_PC, issue_if.rs2_is_imm, issue_if.ex_type, issue_if.ex_op, issue_if.wb, issue_if.frm, issue_if.tid})
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);
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assign decode_if.ready = issue_if.ready;
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assign issue_if.ready = ~stall;
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VX_issue_demux issue_demux (
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.issue_if (issue_if),
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.alu_req_if (alu_req_if),
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.bru_req_if (bru_req_if),
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.lsu_req_if (lsu_req_if),
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.csr_req_if (csr_req_if),
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.mul_req_if (mul_req_if),
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.fpu_req_if (fpu_req_if),
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.gpu_req_if (gpu_req_if)
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_req_if.valid && alu_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=ALU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, alu_req_if.wid, alu_req_if.curr_PC, alu_req_if.issue_tag, alu_req_if.thread_mask, alu_req_if.rs1_data, alu_req_if.rs2_data);
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end
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if (bru_req_if.valid && bru_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=BRU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h, offset=%0h", $time, CORE_ID, bru_req_if.wid, bru_req_if.curr_PC, bru_req_if.issue_tag, bru_req_if.thread_mask, bru_req_if.rs1_data, bru_req_if.rs2_data, bru_req_if.offset);
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end
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if (lsu_req_if.valid && lsu_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=LSU, istag=%0d, tmask=%b, rw=%b, byteen=%b, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.wid, lsu_req_if.curr_PC, lsu_req_if.issue_tag, lsu_req_if.thread_mask, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
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end
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if (csr_req_if.valid && csr_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=CSR, istag=%0d, tmask=%b, addr=%0h, mask=%0h", $time, CORE_ID, csr_req_if.wid, csr_req_if.curr_PC, csr_req_if.issue_tag, csr_req_if.thread_mask, csr_req_if.csr_addr, csr_req_if.csr_mask);
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end
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if (mul_req_if.valid && mul_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=MUL, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, mul_req_if.wid, mul_req_if.curr_PC, mul_req_if.issue_tag, mul_req_if.thread_mask, mul_req_if.rs1_data, mul_req_if.rs2_data);
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end
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if (fpu_req_if.valid && fpu_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=FPU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h, rs3_data=%0h", $time, CORE_ID, fpu_req_if.wid, fpu_req_if.curr_PC, fpu_req_if.issue_tag, fpu_req_if.thread_mask, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data);
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end
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if (gpu_req_if.valid && gpu_req_if.ready) begin
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$display("%t: Core%0d-issue: wid=%0d, PC=%0h, ex=GPU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, gpu_req_if.wid, gpu_req_if.curr_PC, gpu_req_if.issue_tag, gpu_req_if.thread_mask, gpu_req_if.rs1_data, gpu_req_if.rs2_data);
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end
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end
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`endif
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endmodule |