115 lines
3.8 KiB
Verilog
115 lines
3.8 KiB
Verilog
`include "VX_define.vh"
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module VX_csr_unit #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_cmt_to_csr_if cmt_to_csr_if,
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VX_csr_to_fpu_if csr_to_fpu_if,
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VX_csr_io_req_if csr_io_req_if,
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VX_csr_io_rsp_if csr_io_rsp_if,
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VX_csr_req_if csr_req_if,
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VX_exu_to_cmt_if csr_commit_if
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);
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VX_csr_req_if csr_pipe_req_if();
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VX_csr_rsp_if csr_pipe_rsp_if();
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wire select_io_req = csr_io_req_if.valid;
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wire select_io_rsp;
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VX_csr_arb csr_arb (
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.clk (clk),
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.reset (reset),
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.csr_core_req_if (csr_req_if),
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.csr_io_req_if (csr_io_req_if),
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.csr_req_if (csr_pipe_req_if),
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.csr_rsp_if (csr_pipe_rsp_if),
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.csr_io_rsp_if (csr_io_rsp_if),
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.csr_commit_if (csr_commit_if),
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.select_io_req (select_io_req),
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.select_io_rsp (select_io_rsp)
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);
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wire csr_we_s1;
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wire [`CSR_ADDR_BITS-1:0] csr_addr_s1;
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wire [31:0] csr_read_data, csr_read_data_s1;
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wire [31:0] csr_updated_data_s1;
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wire [`NW_BITS-1:0] wid_s1;
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VX_csr_data #(
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.CORE_ID(CORE_ID)
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) csr_data (
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.clk (clk),
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.reset (reset),
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.cmt_to_csr_if (cmt_to_csr_if),
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.csr_to_fpu_if (csr_to_fpu_if),
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.read_enable (csr_pipe_req_if.valid),
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.read_addr (csr_pipe_req_if.csr_addr),
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.read_data (csr_read_data),
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.write_enable (csr_we_s1),
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.write_data (csr_updated_data_s1[`CSR_WIDTH-1:0]),
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.write_addr (csr_addr_s1),
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.wid (csr_pipe_req_if.wid)
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);
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wire csr_hazard = (csr_addr_s1 == csr_pipe_req_if.csr_addr)
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&& (wid_s1 == csr_pipe_req_if.wid)
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&& csr_pipe_rsp_if.valid;
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wire [31:0] csr_read_data_qual = csr_hazard ? csr_updated_data_s1 : csr_read_data;
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reg [31:0] csr_updated_data;
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reg csr_we_s0_unqual;
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always @(*) begin
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csr_we_s0_unqual = 0;
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case (csr_pipe_req_if.op)
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`CSR_RW: begin
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csr_updated_data = csr_pipe_req_if.csr_mask;
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csr_we_s0_unqual = 1;
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end
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`CSR_RS: begin
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csr_updated_data = csr_read_data_qual | csr_pipe_req_if.csr_mask;
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csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0);
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end
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`CSR_RC: begin
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csr_updated_data = csr_read_data_qual & (32'hFFFFFFFF - csr_pipe_req_if.csr_mask);
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csr_we_s0_unqual = (csr_pipe_req_if.csr_mask != 0);
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end
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default: csr_updated_data = 32'hdeadbeef;
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endcase
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end
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wire csr_we_s0 = csr_we_s0_unqual && csr_pipe_req_if.valid;
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wire stall = ~csr_pipe_rsp_if.ready && csr_pipe_rsp_if.valid;
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 1 + `CSR_ADDR_BITS + 1 + 32 + 32)
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) csr_reg (
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.clk (clk),
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.reset (reset),
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.stall (stall),
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.flush (0),
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.in ({csr_pipe_req_if.valid, csr_pipe_req_if.issue_tag, csr_pipe_req_if.wid, csr_we_s0, csr_pipe_req_if.csr_addr, csr_pipe_req_if.is_io, csr_read_data_qual, csr_updated_data}),
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.out ({csr_pipe_rsp_if.valid, csr_pipe_rsp_if.issue_tag, wid_s1, csr_we_s1, csr_addr_s1, select_io_rsp, csr_read_data_s1, csr_updated_data_s1})
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);
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for (genvar i = 0; i < `NUM_THREADS; i++) begin
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assign csr_pipe_rsp_if.data[i] = (csr_addr_s1 == `CSR_LTID) ? i :
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(csr_addr_s1 == `CSR_GTID) ? (csr_read_data_s1 * `NUM_THREADS + i) :
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csr_read_data_s1;
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end
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assign csr_pipe_req_if.ready = ~stall;
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endmodule
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