d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
106 lines
2.2 KiB
C++
106 lines
2.2 KiB
C++
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "VVX_cache.h"
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#include "VVX_cache__Syms.h"
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#include "verilated.h"
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//#ifdef VCD_OUTPUT
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#include <verilated_vcd_c.h>
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//#endif
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//#include <VX_config.h>
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#include "ram.h"
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#include <ostream>
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#include <vector>
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#include <queue>
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#define ENABLE_MEM_STALLS
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#define MEM_LATENCY 100
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#define MEM_RQ_SIZE 16
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#define MEM_STALLS_MODULO 16
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#define MEM_BLOCK_SIZE 16
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typedef struct {
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int cycles_left;
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uint8_t *data;
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unsigned tag;
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} mem_req_t;
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typedef struct {
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char valid;
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char rw;
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unsigned byteen;
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unsigned *addr;
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unsigned *data;
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unsigned int tag;
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} core_req_t;
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class CacheSim {
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public:
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CacheSim();
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virtual ~CacheSim();
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bool busy();
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void reset();
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void step();
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void wait(uint32_t cycles);
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void attach_ram(RAM* ram);
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void run(); //run until all reqs are empty
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//req/rsp
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void send_req(core_req_t *req);
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void clear_req();
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void stall_mem();
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void send_snoop_req();
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void send_snp_fwd_in();
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//assert funcs
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bool assert_equal(unsigned int* data, unsigned int tag);
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//debug funcs
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void get_mem_req();
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void get_core_req(unsigned int (&rsp)[4]);
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void get_core_rsp();
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bool get_core_req_ready();
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bool get_core_rsp_ready();
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void get_mem_rsp();
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void display_miss();
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private:
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void eval();
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void eval_reqs();
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void eval_rsps();
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void eval_mem_bus();
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std::queue<core_req_t*> core_req_vec_;
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std::vector<mem_req_t> mem_rsp_vec_;
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std::map<unsigned int, unsigned int*> core_rsp_vec_;
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int mem_rsp_active_;
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uint32_t snp_req_active_;
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uint32_t snp_req_size_;
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uint32_t pending_snp_reqs_;
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VVX_cache *cache_;
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RAM *ram_;
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//#ifdef VCD_OUTPUT
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VerilatedVcdC *trace_;
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//#endif
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};
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