131 lines
4.4 KiB
Verilog
131 lines
4.4 KiB
Verilog
`include "VX_cache_config.vh"
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module VX_snp_forwarder #(
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parameter BANK_LINE_SIZE = 0,
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parameter NUM_REQUESTS = 0,
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parameter SNRQ_SIZE = 0,
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parameter SNP_REQ_TAG_WIDTH = 0,
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parameter SNP_FWD_TAG_WIDTH = 0
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) (
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input wire clk,
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input wire reset,
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// Snoop request
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input wire snp_req_valid,
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input wire [`DRAM_ADDR_WIDTH-1:0] snp_req_addr,
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input wire [SNP_REQ_TAG_WIDTH-1:0] snp_req_tag,
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output wire snp_req_ready,
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// Snoop response
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output wire snp_rsp_valid,
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output wire [`DRAM_ADDR_WIDTH-1:0] snp_rsp_addr,
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output wire [SNP_REQ_TAG_WIDTH-1:0] snp_rsp_tag,
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input wire snp_rsp_ready,
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// Snoop Forwarding out
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output wire [NUM_REQUESTS-1:0] snp_fwdout_valid,
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output wire [NUM_REQUESTS-1:0][`DRAM_ADDR_WIDTH-1:0] snp_fwdout_addr,
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output wire [NUM_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdout_tag,
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input wire [NUM_REQUESTS-1:0] snp_fwdout_ready,
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// Snoop forwarding in
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input wire [NUM_REQUESTS-1:0] snp_fwdin_valid,
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input wire [NUM_REQUESTS-1:0][SNP_FWD_TAG_WIDTH-1:0] snp_fwdin_tag,
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output wire [NUM_REQUESTS-1:0] snp_fwdin_ready
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);
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reg [`DRAM_ADDR_WIDTH+SNP_REQ_TAG_WIDTH-1:0] pending_reqs [SNRQ_SIZE-1:0];
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reg [`REQS_BITS-1:0] pending_cntrs [SNRQ_SIZE-1:0];
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reg [`LOG2UP(SNRQ_SIZE)-1:0] rd_ptr, wr_ptr;
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reg [`LOG2UP(SNRQ_SIZE)-1:0] pending_size;
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reg [`REQS_BITS-1:0] fwdin_sel;
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wire enqueue, dequeue;
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wire fwdout_ready;
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wire fwdin_valid;
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wire [SNP_FWD_TAG_WIDTH-1:0] fwdin_tag;
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wire fwdin_ready;
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wire fwdin_taken;
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assign fwdout_ready = (& snp_fwdout_ready);
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assign snp_req_ready = (pending_size != `LOG2UP(SNRQ_SIZE)'(SNRQ_SIZE-1)) // not full
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&& fwdout_ready;
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genvar i;
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign snp_fwdout_valid[i] = enqueue && fwdout_ready;
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assign snp_fwdout_addr[i] = snp_req_addr;
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assign snp_fwdout_tag[i] = wr_ptr;
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end
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assign fwdin_ready = snp_rsp_ready;
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assign fwdin_taken = fwdin_valid && fwdin_ready;
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assign snp_rsp_valid = fwdin_taken && (1 == pending_cntrs[fwdin_tag]); // send response
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assign {snp_rsp_addr, snp_rsp_tag} = pending_reqs[fwdin_tag];
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assign enqueue = snp_req_valid && snp_req_ready;
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assign dequeue = snp_rsp_valid && (rd_ptr == fwdin_tag);
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always @(posedge clk) begin
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if (reset) begin
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rd_ptr <= 0;
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wr_ptr <= 0;
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pending_size <= 0;
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end else begin
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if (enqueue) begin
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pending_reqs[wr_ptr] <= {snp_req_addr, snp_req_tag};
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pending_cntrs[wr_ptr] <= `REQS_BITS'(NUM_REQUESTS);
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wr_ptr <= wr_ptr + 1;
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if (!dequeue) begin
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pending_size <= pending_size + 1;
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end
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end
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if (dequeue) begin
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rd_ptr <= rd_ptr + 1;
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if (!enqueue) begin
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pending_size <= pending_size - 1;
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end
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end
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if (fwdin_taken) begin
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pending_cntrs[fwdin_tag] <= pending_cntrs[fwdin_tag] - 1;
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end
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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fwdin_sel <= 0;
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end else begin
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fwdin_sel <= fwdin_sel + 1;
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end
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end
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assign fwdin_valid = snp_fwdin_valid[fwdin_sel];
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assign fwdin_tag = snp_fwdin_tag[fwdin_sel];
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for (i = 0; i < NUM_REQUESTS; i++) begin
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assign snp_fwdin_ready[i] = fwdin_ready && (fwdin_sel == `REQS_BITS'(i));
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end
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`ifdef DBG_PRINT_CACHE_SNP
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always_ff @(posedge clk) begin
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if (snp_req_valid && snp_req_ready) begin
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$display("%t: snp req: addr=%0h, tag=%0h", $time, snp_req_addr, snp_req_tag);
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end
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if (snp_fwdout_valid[0] && snp_fwdout_ready[0]) begin
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$display("%t: snp fwd_out: addr=%0h, tag=%0h", $time, snp_fwdout_addr[0], snp_fwdout_tag[0]);
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end
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if (fwdin_valid && fwdin_ready) begin
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$display("%t: snp fwd_in[%01d]: tag=%0h", $time, fwdin_sel, fwdin_tag);
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end
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if (snp_rsp_valid && snp_rsp_ready) begin
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$display("%t: snp rsp: addr=%0h, tag=%0h", $time, snp_rsp_addr, snp_rsp_tag);
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end
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end
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`endif
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endmodule |