251 lines
8.2 KiB
Verilog
251 lines
8.2 KiB
Verilog
`include "VX_define.vh"
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module VX_execute #(
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parameter CORE_ID = 0
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) (
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`SCOPE_IO_VX_execute
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input wire clk,
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input wire reset,
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// Dcache interface
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VX_dcache_req_if dcache_req_if,
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VX_dcache_rsp_if dcache_rsp_if,
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// commit status
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VX_cmt_to_csr_if cmt_to_csr_if,
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`ifdef PERF_ENABLE
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VX_perf_memsys_if perf_memsys_if,
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VX_perf_pipeline_if perf_pipeline_if,
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`endif
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// inputs
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if,
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// outputs
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VX_branch_ctl_if branch_ctl_if,
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VX_warp_ctl_if warp_ctl_if,
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VX_commit_if alu_commit_if,
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VX_commit_if ld_commit_if,
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VX_commit_if st_commit_if,
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VX_commit_if csr_commit_if,
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VX_commit_if fpu_commit_if,
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VX_commit_if gpu_commit_if,
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input wire busy
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);
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VX_fpu_to_csr_if fpu_to_csr_if();
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`ifdef EXT_TEX_ENABLE
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VX_dcache_req_if #(
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.NUM_REQS (`NUM_THREADS),
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.WORD_SIZE (4),
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.TAG_WIDTH (`LSU_DCACHE_TAG_BITS)
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) lsu_dcache_req_if();
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VX_dcache_rsp_if #(
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.NUM_REQS (`NUM_THREADS),
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.WORD_SIZE (4),
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.TAG_WIDTH (`LSU_DCACHE_TAG_BITS)
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) lsu_dcache_rsp_if();
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VX_dcache_req_if #(
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.NUM_REQS (`NUM_THREADS),
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.WORD_SIZE (4),
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.TAG_WIDTH (`TEX_DCACHE_TAG_BITS)
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) tex_dcache_req_if();
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VX_dcache_rsp_if #(
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.NUM_REQS (`NUM_THREADS),
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.WORD_SIZE (4),
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.TAG_WIDTH (`TEX_DCACHE_TAG_BITS)
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) tex_dcache_rsp_if();
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VX_tex_csr_if tex_csr_if();
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wire [`NUM_THREADS-1:0][`LSU_TEX_DCACHE_TAG_BITS-1:0] tex_tag_in, lsu_tag_in;
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wire [`LSU_TEX_DCACHE_TAG_BITS-1:0] tex_tag_out, lsu_tag_out;
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`UNUSED_VAR (tex_tag_out)
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`UNUSED_VAR (lsu_tag_out)
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for (genvar i = 0; i < `NUM_THREADS; ++i) begin
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assign tex_tag_in[i][`LSU_TEX_TAG_ID_BITS-1:0] = `LSU_TEX_TAG_ID_BITS'(tex_dcache_req_if.tag[i][`TEX_TAG_ID_BITS-1:0]);
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assign lsu_tag_in[i][`LSU_TEX_TAG_ID_BITS-1:0] = `LSU_TEX_TAG_ID_BITS'(lsu_dcache_req_if.tag[i][`LSU_TAG_ID_BITS-1:0]);
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`ifdef DBG_CACHE_REQ_INFO
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assign tex_tag_in[i][`LSU_TEX_DCACHE_TAG_BITS-1:`LSU_TEX_TAG_ID_BITS] = tex_dcache_req_if.tag[i][`TEX_DCACHE_TAG_BITS-1:`TEX_TAG_ID_BITS];
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assign lsu_tag_in[i][`LSU_TEX_DCACHE_TAG_BITS-1:`LSU_TEX_TAG_ID_BITS] = lsu_dcache_req_if.tag[i][`LSU_DCACHE_TAG_BITS-1:`LSU_TAG_ID_BITS];
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`endif
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end
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assign tex_dcache_rsp_if.tag[`TEX_TAG_ID_BITS-1:0] = tex_tag_out[`TEX_TAG_ID_BITS-1:0];
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assign lsu_dcache_rsp_if.tag[`LSU_TAG_ID_BITS-1:0] = lsu_tag_out[`LSU_TAG_ID_BITS-1:0];
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`ifdef DBG_CACHE_REQ_INFO
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assign tex_dcache_rsp_if.tag[`TEX_DCACHE_TAG_BITS-1:`TEX_TAG_ID_BITS] = tex_tag_out[`LSU_TEX_DCACHE_TAG_BITS-1:`LSU_TEX_TAG_ID_BITS];
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assign lsu_dcache_rsp_if.tag[`LSU_DCACHE_TAG_BITS-1:`LSU_TAG_ID_BITS] = lsu_tag_out[`LSU_TEX_DCACHE_TAG_BITS-1:`LSU_TEX_TAG_ID_BITS];
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`endif
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VX_cache_arb #(
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.NUM_REQS (2),
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.LANES (`NUM_THREADS),
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.DATA_SIZE (4),
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.TAG_IN_WIDTH (`LSU_TEX_DCACHE_TAG_BITS),
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.TAG_SEL_IDX (`NC_ADDR_BITS + `SM_ENABLE)
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) tex_lsu_arb (
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.clk (clk),
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.reset (reset),
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// Tex/LSU request
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.req_valid_in ({tex_dcache_req_if.valid, lsu_dcache_req_if.valid}),
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.req_rw_in ({tex_dcache_req_if.rw, lsu_dcache_req_if.rw}),
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.req_byteen_in ({tex_dcache_req_if.byteen, lsu_dcache_req_if.byteen}),
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.req_addr_in ({tex_dcache_req_if.addr, lsu_dcache_req_if.addr}),
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.req_data_in ({tex_dcache_req_if.data, lsu_dcache_req_if.data}),
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.req_tag_in ({tex_tag_in, lsu_tag_in}),
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.req_ready_in ({tex_dcache_req_if.ready, lsu_dcache_req_if.ready}),
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// Dcache request
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.req_valid_out (dcache_req_if.valid),
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.req_rw_out (dcache_req_if.rw),
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.req_byteen_out (dcache_req_if.byteen),
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.req_addr_out (dcache_req_if.addr),
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.req_data_out (dcache_req_if.data),
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.req_tag_out (dcache_req_if.tag),
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.req_ready_out (dcache_req_if.ready),
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// Dcache response
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.rsp_valid_in (dcache_rsp_if.valid),
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.rsp_tmask_in (dcache_rsp_if.tmask),
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.rsp_tag_in (dcache_rsp_if.tag),
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.rsp_data_in (dcache_rsp_if.data),
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.rsp_ready_in (dcache_rsp_if.ready),
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// Tex/LSU response
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.rsp_valid_out ({tex_dcache_rsp_if.valid, lsu_dcache_rsp_if.valid}),
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.rsp_tmask_out ({tex_dcache_rsp_if.tmask, lsu_dcache_rsp_if.tmask}),
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.rsp_data_out ({tex_dcache_rsp_if.data, lsu_dcache_rsp_if.data}),
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.rsp_tag_out ({tex_tag_out, lsu_tag_out}),
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.rsp_ready_out ({tex_dcache_rsp_if.ready, lsu_dcache_rsp_if.ready})
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);
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`endif
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wire [`NUM_WARPS-1:0] csr_pending;
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wire [`NUM_WARPS-1:0] fpu_pending;
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`RESET_RELAY (alu_reset);
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`RESET_RELAY (lsu_reset);
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`RESET_RELAY (csr_reset);
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`RESET_RELAY (gpu_reset);
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VX_alu_unit #(
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.CORE_ID(CORE_ID)
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) alu_unit (
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.clk (clk),
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.reset (alu_reset),
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.alu_req_if (alu_req_if),
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.branch_ctl_if (branch_ctl_if),
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.alu_commit_if (alu_commit_if)
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);
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VX_lsu_unit #(
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.CORE_ID(CORE_ID)
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) lsu_unit (
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`SCOPE_BIND_VX_execute_lsu_unit
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.clk (clk),
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.reset (lsu_reset),
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`ifdef EXT_TEX_ENABLE
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.dcache_req_if (lsu_dcache_req_if),
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.dcache_rsp_if (lsu_dcache_rsp_if),
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`else
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.dcache_req_if (dcache_req_if),
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.dcache_rsp_if (dcache_rsp_if),
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`endif
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.lsu_req_if (lsu_req_if),
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.ld_commit_if (ld_commit_if),
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.st_commit_if (st_commit_if)
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);
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VX_csr_unit #(
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.CORE_ID(CORE_ID)
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) csr_unit (
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.clk (clk),
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.reset (csr_reset),
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`ifdef PERF_ENABLE
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.perf_memsys_if (perf_memsys_if),
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.perf_pipeline_if (perf_pipeline_if),
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`endif
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.cmt_to_csr_if (cmt_to_csr_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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`ifdef EXT_TEX_ENABLE
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.tex_csr_if (tex_csr_if),
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`endif
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.csr_req_if (csr_req_if),
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.csr_commit_if (csr_commit_if),
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.fpu_pending (fpu_pending),
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.pending (csr_pending),
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.busy (busy)
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);
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`ifdef EXT_F_ENABLE
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`RESET_RELAY (fpu_reset);
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VX_fpu_unit #(
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.CORE_ID(CORE_ID)
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) fpu_unit (
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.clk (clk),
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.reset (fpu_reset),
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.fpu_req_if (fpu_req_if),
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.fpu_to_csr_if (fpu_to_csr_if),
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.fpu_commit_if (fpu_commit_if),
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.csr_pending (csr_pending),
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.pending (fpu_pending)
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);
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`else
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`UNUSED_VAR (csr_pending)
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`UNUSED_VAR (fpu_to_csr_if.read_frm)
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assign fpu_req_if.ready = 0;
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assign fpu_commit_if.valid = 0;
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assign fpu_commit_if.wid = 0;
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assign fpu_commit_if.PC = 0;
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assign fpu_commit_if.tmask = 0;
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assign fpu_commit_if.wb = 0;
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assign fpu_commit_if.rd = 0;
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assign fpu_commit_if.data = 0;
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assign fpu_to_csr_if.write_enable = 0;
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assign fpu_to_csr_if.write_wid = 0;
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assign fpu_to_csr_if.write_fflags = 0;
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assign fpu_to_csr_if.read_wid = 0;
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assign fpu_pending = 0;
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`endif
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VX_gpu_unit #(
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.CORE_ID(CORE_ID)
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) gpu_unit (
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`SCOPE_BIND_VX_execute_gpu_unit
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.clk (clk),
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.reset (gpu_reset),
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.gpu_req_if (gpu_req_if),
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`ifdef EXT_TEX_ENABLE
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.tex_csr_if (tex_csr_if),
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.dcache_req_if (tex_dcache_req_if),
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.dcache_rsp_if (tex_dcache_rsp_if),
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`endif
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.warp_ctl_if (warp_ctl_if),
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.gpu_commit_if (gpu_commit_if)
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);
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// special workaround to get RISC-V tests Pass/Fail status
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wire ebreak /* verilator public */;
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assign ebreak = alu_req_if.valid && alu_req_if.ready
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&& `ALU_IS_BR(alu_req_if.op_mod)
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&& (`BR_OP(alu_req_if.op_type) == `BR_EBREAK
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|| `BR_OP(alu_req_if.op_type) == `BR_ECALL);
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endmodule |