28 lines
1.4 KiB
Plaintext
28 lines
1.4 KiB
Plaintext
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# Analysis & Synthesis Assignments
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
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set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS ON
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set_global_assignment -name VERILOG_MACRO QUARTUS
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set_global_assignment -name VERILOG_MACRO SYNTHESIS
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set_global_assignment -name VERILOG_MACRO NDEBUG
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set_global_assignment -name MESSAGE_DISABLE 16818
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set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
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#set_global_assignment -name OPTIMIZATION_TECHNIQUE BALANCED
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#set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
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#set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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#set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
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#set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
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#set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
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#set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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#set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
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#set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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#set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
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#set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
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#set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
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#set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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#set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
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#set_global_assignment -name POWER_USE_TA_VALUE 65
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#set_global_assignment -name SEED 1 |