56 lines
1.4 KiB
Verilog
56 lines
1.4 KiB
Verilog
`include "VX_define.vh"
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module VX_matrix_arbiter #(
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parameter N = 0
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) (
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input wire clk,
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input wire reset,
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input wire [N-1:0] inputs,
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output wire [N-1:0] grant
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);
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reg [N-1:1][N-1:0] pri;
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always @(posedge clk) begin
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if (reset) begin
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integer i, j;
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for (i = 0; i < N; ++i) begin
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for (j = 0; j < N; ++j) begin
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pri[i][j] <= 1;
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end
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end
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end else begin
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integer i, j;
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for (i = 0; i < N; ++i) begin
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if (grant[i]) begin
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for (j = 0; j < N; ++j) begin
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if (j > i)
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pri[j][i] <= 1;
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else if (j < i)
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pri[i][j] <= 0;
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end
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end
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end
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end
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end
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genvar i, j;
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for (i = 0; i < N; ++i) begin
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wire [N-1:0] dis;
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for (j = 0; j < N; ++j) begin
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if (j > i) begin
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assign dis[j] = inputs[j] & pri[j][i];
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end else if (j < i) begin
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assign dis[j] = inputs[j] & ~pri[i][j];
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end else begin
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assign dis[j] = 0;
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end
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end
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assign grant[i] = inputs[i] & ~(| dis);
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end
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endmodule |