180 lines
9.7 KiB
Verilog
180 lines
9.7 KiB
Verilog
`include "VX_define.vh"
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module VX_issue #(
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parameter CORE_ID = 0
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) (
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input wire clk,
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input wire reset,
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VX_decode_if decode_if,
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VX_wb_if writeback_if,
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VX_cmt_to_issue_if cmt_to_issue_if,
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VX_alu_req_if alu_req_if,
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VX_lsu_req_if lsu_req_if,
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VX_csr_req_if csr_req_if,
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VX_mul_req_if mul_req_if,
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VX_fpu_req_if fpu_req_if,
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VX_gpu_req_if gpu_req_if
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);
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wire [`ISTAG_BITS-1:0] issue_tag;
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wire schedule_delay;
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VX_gpr_read_if gpr_read_if();
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assign gpr_read_if.valid = decode_if.valid && ~schedule_delay;
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assign gpr_read_if.warp_num = decode_if.warp_num;
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assign gpr_read_if.rs1 = decode_if.rs1;
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assign gpr_read_if.rs2 = decode_if.rs2;
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assign gpr_read_if.rs3 = decode_if.rs3;
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assign gpr_read_if.use_rs3 = decode_if.use_rs3;
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wire ex_busy = (~alu_req_if.ready && (decode_if.ex_type == `EX_ALU))
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|| (~lsu_req_if.ready && (decode_if.ex_type == `EX_LSU))
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|| (~csr_req_if.ready && (decode_if.ex_type == `EX_CSR))
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`ifdef EXT_M_ENABLE
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|| (~mul_req_if.ready && (decode_if.ex_type == `EX_MUL))
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`endif
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`ifdef EXT_F_ENABLE
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|| (~fpu_req_if.ready && (decode_if.ex_type == `EX_FPU))
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`endif
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|| (~gpu_req_if.ready && (decode_if.ex_type == `EX_GPU));
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VX_scheduler #(
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.CORE_ID(CORE_ID)
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) scheduler (
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.clk (clk),
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.reset (reset),
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.decode_if (decode_if),
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.writeback_if (writeback_if),
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.cmt_to_issue_if(cmt_to_issue_if),
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.ex_busy (ex_busy),
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.issue_tag (issue_tag),
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.schedule_delay (schedule_delay)
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);
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VX_gpr_stage #(
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.CORE_ID(CORE_ID)
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) gpr_stage (
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.clk (clk),
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.reset (reset),
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.writeback_if (writeback_if),
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.gpr_read_if (gpr_read_if)
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);
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VX_alu_req_if alu_req_tmp_if();
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VX_lsu_req_if lsu_req_tmp_if();
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VX_csr_req_if csr_req_tmp_if();
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VX_mul_req_if mul_req_tmp_if();
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VX_fpu_req_if fpu_req_tmp_if();
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VX_gpu_req_if gpu_req_tmp_if();
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VX_issue_demux issue_demux (
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.decode_if (decode_if),
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.gpr_read_if(gpr_read_if),
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.issue_tag (issue_tag),
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.alu_req_if (alu_req_tmp_if),
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.lsu_req_if (lsu_req_tmp_if),
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.csr_req_if (csr_req_tmp_if),
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.mul_req_if (mul_req_tmp_if),
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.fpu_req_if (fpu_req_tmp_if),
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.gpu_req_if (gpu_req_tmp_if)
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);
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wire stall = schedule_delay || ~gpr_read_if.ready;
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assign decode_if.ready = ~stall;
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 32 + `NUM_THREADS + `ALU_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32) + 32 + 32)
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) alu_reg (
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.clk (clk),
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.reset (reset),
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.stall (~alu_req_if.ready),
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.flush (stall && alu_req_if.ready),
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.in ({alu_req_tmp_if.valid, alu_req_tmp_if.issue_tag, alu_req_tmp_if.warp_num, alu_req_tmp_if.curr_PC, alu_req_tmp_if.thread_mask, alu_req_tmp_if.alu_op, alu_req_tmp_if.rs1_data, alu_req_tmp_if.rs2_data, alu_req_tmp_if.offset, alu_req_tmp_if.next_PC}),
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.out ({alu_req_if.valid, alu_req_if.issue_tag, alu_req_if.warp_num, alu_req_if.curr_PC, alu_req_if.thread_mask, alu_req_if.alu_op, alu_req_if.rs1_data, alu_req_if.rs2_data, alu_req_if.offset, alu_req_if.next_PC})
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);
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 32 + `NUM_THREADS + 1 + `BYTEEN_BITS + (`NUM_THREADS * 32) + 32 + (`NUM_THREADS * 32) + `NR_BITS + 1)
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) lsu_reg (
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.clk (clk),
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.reset (reset),
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.stall (~lsu_req_if.ready),
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.flush (stall && lsu_req_if.ready),
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.in ({lsu_req_tmp_if.valid, lsu_req_tmp_if.issue_tag, lsu_req_tmp_if.warp_num, lsu_req_tmp_if.curr_PC, lsu_req_tmp_if.thread_mask, lsu_req_tmp_if.rw, lsu_req_tmp_if.byteen, lsu_req_tmp_if.base_addr, lsu_req_tmp_if.offset, lsu_req_tmp_if.store_data, lsu_req_tmp_if.rd, lsu_req_tmp_if.wb}),
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.out ({lsu_req_if.valid, lsu_req_if.issue_tag, lsu_req_if.warp_num, lsu_req_if.curr_PC, lsu_req_if.thread_mask, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data, lsu_req_if.rd, lsu_req_if.wb})
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);
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 32 + `NUM_THREADS + `CSR_BITS + `CSR_ADDR_BITS + 32 + 1)
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) csr_reg (
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.clk (clk),
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.reset (reset),
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.stall (~csr_req_if.ready),
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.flush (stall && csr_req_if.ready),
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.in ({csr_req_tmp_if.valid, csr_req_tmp_if.issue_tag, csr_req_tmp_if.warp_num, csr_req_tmp_if.curr_PC, csr_req_tmp_if.thread_mask, csr_req_tmp_if.csr_op, csr_req_tmp_if.csr_addr, csr_req_tmp_if.csr_mask, csr_req_tmp_if.is_io}),
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.out ({csr_req_if.valid, csr_req_if.issue_tag, csr_req_if.warp_num, csr_req_if.curr_PC, csr_req_if.thread_mask, csr_req_if.csr_op, csr_req_if.csr_addr, csr_req_if.csr_mask, csr_req_if.is_io})
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);
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`ifdef EXT_M_ENABLE
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 32 + `NUM_THREADS + `MUL_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32))
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) mul_reg (
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.clk (clk),
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.reset (reset),
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.stall (~mul_req_if.ready),
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.flush (stall && mul_req_if.ready),
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.in ({mul_req_tmp_if.valid, mul_req_tmp_if.issue_tag, mul_req_tmp_if.warp_num, mul_req_tmp_if.curr_PC, mul_req_tmp_if.thread_mask, mul_req_tmp_if.mul_op, mul_req_tmp_if.rs1_data, mul_req_tmp_if.rs2_data}),
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.out ({mul_req_if.valid, mul_req_if.issue_tag, mul_req_if.warp_num, mul_req_if.curr_PC, mul_req_if.thread_mask, mul_req_if.mul_op, mul_req_if.rs1_data, mul_req_if.rs2_data})
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);
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`endif
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`ifdef EXT_F_ENABLE
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 32 + `NUM_THREADS + `FPU_BITS + `FRM_BITS + (`NUM_THREADS * 32) + (`NUM_THREADS * 32) + (`NUM_THREADS * 32))
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) fpu_reg (
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.clk (clk),
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.reset (reset),
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.stall (~fpu_req_if.ready),
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.flush (stall && fpu_req_if.ready),
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.in ({fpu_req_tmp_if.valid, fpu_req_tmp_if.issue_tag, fpu_req_tmp_if.warp_num, fpu_req_tmp_if.curr_PC, fpu_req_tmp_if.thread_mask, fpu_req_tmp_if.fpu_op, fpu_req_tmp_if.frm, fpu_req_tmp_if.rs1_data, fpu_req_tmp_if.rs2_data, fpu_req_tmp_if.rs3_data}),
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.out ({fpu_req_if.valid, fpu_req_if.issue_tag, fpu_req_if.warp_num, fpu_req_if.curr_PC, fpu_req_if.thread_mask, fpu_req_if.fpu_op, fpu_req_if.frm, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data})
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);
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`endif
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VX_generic_register #(
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.N(1 + `ISTAG_BITS + `NW_BITS + 32 + `NUM_THREADS + `GPU_BITS + (`NUM_THREADS * 32) + 32 + 32)
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) gpu_reg (
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.clk (clk),
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.reset (reset),
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.stall (~gpu_req_if.ready),
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.flush (stall && gpu_req_if.ready),
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.in ({gpu_req_tmp_if.valid, gpu_req_tmp_if.issue_tag, gpu_req_tmp_if.warp_num, gpu_req_tmp_if.curr_PC, gpu_req_tmp_if.thread_mask, gpu_req_tmp_if.gpu_op, gpu_req_tmp_if.rs1_data, gpu_req_tmp_if.rs2_data, gpu_req_tmp_if.next_PC}),
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.out ({gpu_req_if.valid, gpu_req_if.issue_tag, gpu_req_if.warp_num, gpu_req_if.curr_PC, gpu_req_if.thread_mask, gpu_req_if.gpu_op, gpu_req_if.rs1_data, gpu_req_if.rs2_data, gpu_req_if.next_PC})
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);
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`ifdef DBG_PRINT_PIPELINE
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always @(posedge clk) begin
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if (alu_req_if.valid && alu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=ALU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h, offset=%0h, next_PC=%0h", $time, CORE_ID, alu_req_if.warp_num, alu_req_if.curr_PC, alu_req_if.issue_tag, alu_req_if.thread_mask, alu_req_if.rs1_data, alu_req_if.rs2_data, alu_req_if.offset, alu_req_if.next_PC);
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end
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if (lsu_req_if.valid && lsu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=LSU, istag=%0d, tmask=%b, rw=%b, byteen=%b, baddr=%0h, offset=%0h, data=%0h", $time, CORE_ID, lsu_req_if.warp_num, lsu_req_if.curr_PC, lsu_req_if.issue_tag, lsu_req_if.thread_mask, lsu_req_if.rw, lsu_req_if.byteen, lsu_req_if.base_addr, lsu_req_if.offset, lsu_req_if.store_data);
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end
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if (csr_req_if.valid && csr_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=CSR, istag=%0d, tmask=%b, addr=%0h, mask=%0h", $time, CORE_ID, csr_req_if.warp_num, csr_req_if.curr_PC, csr_req_if.issue_tag, csr_req_if.thread_mask, csr_req_if.csr_addr, csr_req_if.csr_mask);
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end
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if (mul_req_if.valid && mul_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=MUL, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, mul_req_if.warp_num, mul_req_if.curr_PC, mul_req_if.issue_tag, mul_req_if.thread_mask, mul_req_if.rs1_data, mul_req_if.rs2_data);
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end
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if (fpu_req_if.valid && fpu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=FPU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h, rs3_data=%0h", $time, CORE_ID, fpu_req_if.warp_num, fpu_req_if.curr_PC, fpu_req_if.issue_tag, fpu_req_if.thread_mask, fpu_req_if.rs1_data, fpu_req_if.rs2_data, fpu_req_if.rs3_data);
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end
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if (gpu_req_if.valid && gpu_req_if.ready) begin
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$display("%t: Core%0d-issue: warp=%0d, PC=%0h, ex=GPU, istag=%0d, tmask=%b, rs1_data=%0h, rs2_data=%0h", $time, CORE_ID, gpu_req_if.warp_num, gpu_req_if.curr_PC, gpu_req_if.issue_tag, gpu_req_if.thread_mask, gpu_req_if.rs1_data, gpu_req_if.rs2_data);
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end
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end
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`endif
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endmodule |