194 lines
6.6 KiB
Verilog
194 lines
6.6 KiB
Verilog
// Cache Memory (8way 4word) //
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// i_ means input port //
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// o_ means output port //
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// _p_ means data exchange with processor //
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// _m_ means data exchange with memory //
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// TO DO:
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// - Send in a response from memory of what the data is from the test bench
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`include "VX_define.v"
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//`include "VX_priority_encoder.v"
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`include "VX_Cache_Bank.v"
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//`include "cache_set.v"
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module VX_d_cache(clk,
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rst,
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i_p_addr,
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//i_p_byte_en,
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i_p_writedata,
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i_p_read_or_write, // 0 = Read | 1 = Write
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i_p_valid,
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//i_p_write,
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o_p_readdata,
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o_p_waitrequest, // 0 = all threads done | 1 = Still threads that need to
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o_m_addr,
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//o_m_byte_en,
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o_m_writedata,
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o_m_read_or_write, // 0 = Read | 1 = Write
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o_m_valid,
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//o_m_write,
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i_m_readdata,
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//i_m_readdata_ready,
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//i_m_waitrequest,
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i_m_ready
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//cnt_r,
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//cnt_w,
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//cnt_hit_r,
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//cnt_hit_w
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//cnt_wb_r,
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//cnt_wb_w
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);
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parameter NUMBER_BANKS = 8;
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localparam CACHE_IDLE = 0; // Idle
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localparam SORT_BY_BANK = 1; // Determines the bank each thread will access
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localparam INITIAL_ACCESS = 2; // Accesses the bank and checks if it is a hit or miss
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localparam INITIAL_PROCESSING = 3; // Check to see if there were misses
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localparam CONTINUED_PROCESSING = 4; // Keep checking status of banks that need to be written back or fetched
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localparam DIRTY_EVICT_GRAB_BLOCK = 5; // Grab the full block of dirty data
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localparam DIRTY_EVICT_WB = 6; // Write back this block into memory
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localparam FETCH_FROM_MEM = 7; // Send a request to mem looking for read data
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localparam FETCH2 = 8; // Stall until memory gets back with the data
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localparam UPDATE_CACHE = 9; // Update the cache with the data read from mem
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localparam RE_ACCESS = 10; // Access the cache after the block has been fetched from memory
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localparam RE_ACCESS_PROCESSING = 11; // Access the cache after the block has been fetched from memory
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//parameter cache_entry = 9;
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input wire clk, rst;
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input wire [`NT_M1:0] i_p_valid;
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//input wire [`NT_M1:0][24:0] i_p_addr; // FIXME
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input wire [`NT_M1:0][31:0] i_p_addr; // FIXME
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input wire i_p_initial_request;
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//input wire [3:0] i_p_byte_en;
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input wire [`NT_M1:0][31:0] i_p_writedata;
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input wire i_p_read_or_write; //, i_p_write;
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output reg [`NT_M1:0][31:0] o_p_readdata;
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output reg [`NT_M1:0] o_p_readdata_valid;
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output wire o_p_waitrequest;
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//output reg [24:0] o_m_addr; // Only one address is sent out at a time to memory -- FIXME
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output reg [31:0] o_m_addr; // Address is xxxxxxxxxxoooobbbyy
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output reg o_m_valid;
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//output wire [255:0][31:0] evicted_data;
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//output wire [3:0] o_m_byte_en;
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//output reg [(NUMBER_BANKS * 32) - 1:0] o_m_writedata;
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output reg[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] o_m_writedata;
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output reg o_m_read_or_write; //, o_m_write;
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//input wire [(NUMBER_BANKS * 32) - 1:0] i_m_readdata; // Read Data that is passed from the memory module back to the controller
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input wire[NUMBER_BANKS - 1:0][`NUM_WORDS_PER_BLOCK-1:0][31:0] i_m_readdata;
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//input wire i_m_readdata_ready;
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//input wire i_m_waitrequest;
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input wire i_m_ready;
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// Actual logic
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reg [3:0] state;
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wire[3:0] new_state;
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reg [`NT_M1:0][31:0] final_data_read;
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wire[`NT_M1:0][31:0] new_final_data_read;
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wire[NUMBER_BANKS-1:0] readdata_per_bank;
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wire[NUMBER_BANKS-1:0] hit_per_bank;
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wire[`NT_M1:0] use_valid;
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reg[`NT_M1:0] stored_valid;
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wire[`NT_M1:0] new_stored_valid;
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wire[NUMBER_BANKS - 1 : 0][$clog2(`NT)-1:0] index_per_bank;
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wire[NUMBER_BANKS - 1 : 0] valid_per_bank;
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assign use_valid = (stored_valid == 0) ? i_p_valid : stored_valid;
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wire[NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks;
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VX_cache_bank_valid #(.NUMBER_BANKS(NUMBER_BANKS)) multip_banks(
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.i_p_valid (use_valid),
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.i_p_addr (i_p_addr),
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.thread_track_banks(thread_track_banks)
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);
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reg detect_bank_conflict;
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genvar bank_ind;
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for (bank_ind = 0; bank_ind < NUMBER_BANKS; bank_ind=bank_ind+1)
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begin
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detect_bank_conflict = detect_bank_conflict | ($countones(thread_track_banks[bank_ind]) > 1);
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VX_generic_priority_encoder #(.N(1)) choose_thread(
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.valids(thread_track_banks[bank_ind]),
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.index (index_per_bank[bank_ind]),
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.found (valid_per_bank[bank_ind])
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);
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////////////////
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assign new_final_data_read[index_per_bank[bank_ind]] = hit_per_bank ? readdata_per_bank[bank_ind] : 0;
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end
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wire[NUMBER_BANKS - 1 : 0] detect_bank_miss = (valid_per_bank & ~hit_per_bank);
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wire delay;
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assign delay = (new_stored_valid != 0); // add other states
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// assign delay = detect_bank_conflict || (|detect_bank_miss) || (state != CACHE_IDLE); // add other states
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wire[NUMBER_BANKS - 1 : 0][$clog2(`NT)-1:0] send_index_to_bank = index_per_bank;
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// End actual logic
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assign new_state = detect_bank_miss ? DIRTY_EVICT_WB : CACHE_IDLE;
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// Handle if there is more than one miss
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assign new_stored_valid = (state == CACHE_IDLE) ? ( & ~hit_per_bank);
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genvar bank_id;
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generate
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for (bank_id = 0; bank_id < NUMBER_BANKS; bank_id = bank_id + 1)
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begin
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wire[31:0] bank_addr = i_p_addr[send_index_to_bank[bank_ind]];
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wire[7:0] cache_index = bank_addr[14:7];
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wire[16:0] cache_tag = bank_addr[31:15];
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wire[1:0] cache_offset = bank_addr[6:5];
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VX_Cache_Bank bank_structure (
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.clk (clk),
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.state (state),
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.valid_in (valid_per_bank[bank_ind])
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.actual_index (cache_index),
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.o_tag (cache_tag),
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.block_offset (cache_offset),
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.writedata (i_p_writedata[send_index_to_bank[bank_ind]]),
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.read_or_write (rd_or_wr),
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.hit (hit_per_bank[bank_ind]),
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.readdata (readdata_per_bank[bank_ind]), // Data read
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.fetched_writedata(fetched_writedata), // From memory
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.eviction_wb (eviction_wb),
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.eviction_addr (eviction_addr),
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.data_evicted (data_evicted)
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);
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end
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endgenerate
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//end
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endmodule |