75 lines
2.6 KiB
Verilog
75 lines
2.6 KiB
Verilog
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`include "VX_define.v"
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module VX_dmem_controller (
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input wire clk,
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input wire reset,
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// MEM-RAM
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VX_dram_req_rsp_inter VX_dram_req_rsp,
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// MEM-Processor
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VX_dcache_request_inter VX_dcache_req,
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VX_dcache_response_inter VX_dcache_rsp
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);
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wire to_shm = VX_dcache_req.out_cache_driver_in_address[0][31:24] == 8'hFF;
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wire[`NT_M1:0] sm_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{to_shm}};
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wire[`NT_M1:0] cache_driver_in_valid = VX_dcache_req.out_cache_driver_in_valid & {`NT{~to_shm}};
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// Cache don't understand
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wire initial_request = (|cache_driver_in_valid);
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wire read_or_write = (VX_dcache_req.out_cache_driver_in_mem_write != `NO_MEM_WRITE);
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wire[`NT_M1:0][31:0] cache_driver_in_address = VX_dcache_req.out_cache_driver_in_address;
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wire[2:0] cache_driver_in_mem_read = VX_dcache_req.out_cache_driver_in_mem_read;
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wire[2:0] cache_driver_in_mem_write = VX_dcache_req.out_cache_driver_in_mem_write;
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wire[`NT_M1:0][31:0] cache_driver_in_data = VX_dcache_req.out_cache_driver_in_data;
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wire[`NT_M1:0][31:0] cache_driver_out_data;
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wire[`NT_M1:0][31:0] sm_driver_out_data;
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wire[`NT_M1:0] cache_driver_out_valid; // Not used for now
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wire sm_delay;
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wire cache_done;
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VX_shared_memory #(.NB(7), .BITS_PER_BANK(3)) shared_memory (
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.clk (clk),
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.in_valid (sm_driver_in_valid),
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.in_address(cache_driver_in_address),
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.in_data (cache_driver_in_data),
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.mem_read (cache_driver_in_mem_read),
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.mem_write (cache_driver_in_mem_write),
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.out_valid (cache_driver_out_valid),
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.out_data (sm_driver_out_data),
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.stall (sm_delay)
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);
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VX_d_cache dcache(
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.clk (clk),
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.rst (reset),
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.i_p_valid (cache_driver_in_valid),
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.i_p_addr (cache_driver_in_address),
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.i_p_writedata (cache_driver_in_data),
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.i_p_read_or_write (read_or_write),
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.o_p_readdata (cache_driver_out_data),
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.o_p_waitrequest (cache_done),
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.o_m_addr (VX_dram_req_rsp.o_m_addr),
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.o_m_valid (VX_dram_req_rsp.o_m_valid),
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.o_m_writedata (VX_dram_req_rsp.o_m_writedata),
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.o_m_read_or_write (VX_dram_req_rsp.o_m_read_or_write),
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.i_m_readdata (VX_dram_req_rsp.i_m_readdata),
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.i_m_ready (VX_dram_req_rsp.i_m_ready)
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);
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assign VX_dcache_rsp.in_cache_driver_out_data = to_shm ? sm_driver_out_data : cache_driver_out_data;
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// assign VX_dcache_rsp.delay = sm_delay;
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assign VX_dcache_rsp.delay = sm_delay || (!cache_done);
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endmodule |