d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
65 lines
1.6 KiB
Systemverilog
65 lines
1.6 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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interface VX_mem_bus_if #(
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parameter DATA_SIZE = 1,
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parameter TAG_WIDTH = 1,
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parameter MEM_ADDR_WIDTH = `MEM_ADDR_WIDTH,
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parameter ADDR_WIDTH = MEM_ADDR_WIDTH - `CLOG2(DATA_SIZE)
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) ();
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typedef struct packed {
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logic rw;
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logic [DATA_SIZE-1:0] byteen;
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logic [ADDR_WIDTH-1:0] addr;
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logic [DATA_SIZE*8-1:0] data;
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logic [TAG_WIDTH-1:0] tag;
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} req_data_t;
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typedef struct packed {
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logic [DATA_SIZE*8-1:0] data;
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logic [TAG_WIDTH-1:0] tag;
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} rsp_data_t;
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logic req_valid;
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req_data_t req_data;
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logic req_ready;
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logic rsp_valid;
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rsp_data_t rsp_data;
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logic rsp_ready;
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modport master (
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output req_valid,
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output req_data,
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input req_ready,
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input rsp_valid,
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input rsp_data,
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output rsp_ready
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);
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modport slave (
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input req_valid,
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input req_data,
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output req_ready,
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output rsp_valid,
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output rsp_data,
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input rsp_ready
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);
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endinterface
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