d47cccc157
+ Microarchitecture optimizations + 64-bit support + Xilinx FPGA support + LLVM-16 support + Refactoring and quality control fixes
73 lines
2.5 KiB
Systemverilog
73 lines
2.5 KiB
Systemverilog
// Copyright © 2019-2023
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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`include "VX_define.vh"
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module VX_gbar_unit #(
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parameter `STRING INSTANCE_ID = ""
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) (
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input wire clk,
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input wire reset,
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VX_gbar_bus_if.slave gbar_bus_if
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);
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`UNUSED_SPARAM (INSTANCE_ID)
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reg [`NB_WIDTH-1:0][`NUM_CORES-1:0] barrier_masks;
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wire [`CLOG2(`NUM_CORES+1)-1:0] active_barrier_count;
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wire [`NUM_CORES-1:0] curr_barrier_mask = barrier_masks[gbar_bus_if.req_id];
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`POP_COUNT(active_barrier_count, curr_barrier_mask);
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`UNUSED_VAR (active_barrier_count)
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reg rsp_valid;
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reg [`NB_WIDTH-1:0] rsp_bar_id;
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always @(posedge clk) begin
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if (reset) begin
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barrier_masks <= '0;
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rsp_valid <= 0;
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end else begin
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if (rsp_valid) begin
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rsp_valid <= 0;
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end
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if (gbar_bus_if.req_valid) begin
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if (active_barrier_count[`NC_WIDTH-1:0] == gbar_bus_if.req_size_m1) begin
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barrier_masks[gbar_bus_if.req_id] <= '0;
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rsp_bar_id <= gbar_bus_if.req_id;
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rsp_valid <= 1;
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end else begin
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barrier_masks[gbar_bus_if.req_id][gbar_bus_if.req_core_id] <= 1;
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end
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end
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end
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end
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assign gbar_bus_if.rsp_valid = rsp_valid;
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assign gbar_bus_if.rsp_id = rsp_bar_id;
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assign gbar_bus_if.req_ready = 1; // global barrier unit is always ready (no dependencies)
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`ifdef DBG_TRACE_GBAR
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always @(posedge clk) begin
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if (gbar_bus_if.req_valid && gbar_bus_if.req_ready) begin
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`TRACE(1, ("%d: %s-acquire: bar_id=%0d, size=%0d, core_id=%0d\n",
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$time, INSTANCE_ID, gbar_bus_if.req_id, gbar_bus_if.req_size_m1, gbar_bus_if.req_core_id));
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end
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if (gbar_bus_if.rsp_valid) begin
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`TRACE(1, ("%d: %s-release: bar_id=%0d\n", $time, INSTANCE_ID, gbar_bus_if.rsp_id));
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end
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end
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`endif
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endmodule
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